Frequently Asked Questions
Hardware
Q: Is there a users manual available?
A: No, there is not. It would be good to have one, but we just don't
have the time to write it now.
The best starting points are:
- Main features list
- Official production documentation: EDA-02530 (schematics, PCB layout)
- Software (pointing to examples of the production test software and firmware)
- VME64x core bus interface
- Mezzanine projects that use the SVEC as carrier board: fmc-delay-1ns-8cha, fmc-tdc, fmc-adc-100m14b4cha
- Other FAQ questions: Is there a FPGA reference design available?
- The somewhat similar SPEC board and its FAQ
Q: Does any FMC card work on the SVEC?
A: No, you cannot use any FMC card. The FMC standard allows many options
in the use of the signals on the FMC connector. Signalling levels,
differential or single ended signals and the level of Vadj may all be
chosen rather freely. And of course there is the major option of using a
High Pin-Count (HPC) or Low Pin-Count (LPC) connector which has, indeed,
less pins than the HPC.
To make the SVEC design simple, we had to make some design choices that
may make it not be compatible the FMC mezzanines you'd like to use.
Notably:
- The card uses an LPC connector
- Vadj is fixed to 2.5 Volt, i.e. the signalling levels are 2.5V LVTTL.
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG
To fully check for compatibility the best thing is to verify, signal by signal, the connections in the schematic of the SVEC and of the mezzanine you want to use. You may let us know once you've done this excercise for a particular mezzanine and we possibly can add it to a list of compatible mezzanines.
Firmware
Q: Is the FPGA programmable from the JTAG header on the board?
A: Yes, both FPGAs are programmable from the JTAG header on the board. After powering down you will loose the configuration.
With this same JTAG header you can also program the Configuration EEPROM
that is connected to the "system FPGA", so that the "system FPGA" can
start up with the firmware that is preloaded into the EEPROM.
The "system FPGA" firmware allows access to the EEPROM from the VME and
also to load the "application FPGA" with a firmware located in the
EEPROM. See the
svec-firmware-manual
for details.
Actually the board will be delivered with the "system FPGA" EEPROM pre-loaded with a VME bus interface (the bootloader). With a program writing over the VME bus one is able to program the "application FPGA" who would then take over the control of the VME bus and disable the "system FPGA".
- Schematics at Project information -> Official production documentation.
- Software using the bootloader
Q: Is there a FPGA reference design available?
A: We have not yet a fully documented reference design. However, the "Golden bitstream" is a good start. This is the code that will be loaded in the "application FPGA" and that is able to read the I2C bus on the mezzanines. For the "system FPGA" you may look at the bootloader
- Golden bitstream manual
- VHDL code Golden version
- VHDL code bootloader
- Default preloaded bitstreams
- All code at the SVEC Repository.
Q: What version of the Xilinx tools are you using?
A: We use Xilinx ISE. Currently versions 13.3 and 14.1 are working fine.
Erik van der Bij, Tom Wlostowski, Matthieu Cattin - 20 August 2013