Review01022012comments
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SVEC schematics review 01-02-2012 and reply
Present: Matthieu Cattin, Erik van der Bij, Tom Wlostowski, Carlos Gil Soriano
Major (Design changes)
General
- The BOM must be seriously reduced! The 'simple' SVEC has now even
many more capacitor and resistor types than the VFC.
- Mostly due to many different voltages requiring voltage dividers
- Remove 1nF and 10nF used for decoupling. Can be replaced by 100nF.
Even if 1nF and 10nF are needed in critical places (PLL filter), do
not use these values in decoupling.
-
what about Xilinx recommendations about decoupling? If one
value is already used, it doesn't increase the cost of
assembly.
- It still simplifies. 100nF is good enough, it's the package size that is most important.
-
what about Xilinx recommendations about decoupling? If one
value is already used, it doesn't increase the cost of
assembly.
JTAG&CONFIG.SchDoc
- The board mustn't contain any jumper, it will reduce the number of
mistakes and questions.
- OK
- The FMC JTAG chain must be connected to the AFPGA (as on the SPEC).
- The JTAG chain with the connector (optionnaly the USB chip) must
only contains the 2 FPGAs.
- OK, in my FMC boards I use FPGAs and wanted to have option of connecting the programming cable.
- The AFPGA boot process must be simplified as follow:
- Only one big Flash is connected to the SFPGA.
- The AFPGA boot mode is always "Slave SPI" and the serial progammation interface is connected to the SFPGA.
- The SFPGA is in charge of booting the AFPGA.
- The muxes can be removed, as well as one of the flash and the
"BOOT_SEL" lines.
-
well, but this makes the booting a lot different than SPEC
:)
- That's right, but makes it simpler.
-
well, but this makes the booting a lot different than SPEC
:)
- The EEPROM connected to the SFPGA can be removed.
-
what about storing the card address?
- VME64x uses geographical adressing.
-
what about storing the card address?
FmcConnector.SchDoc
- Add more decoupling capacitors.
- OK
VmeConnector.SchDoc
- Remove all BI power rails (V15N0BI, V5N2BI, V2N0BI, V5P0BI,
V15P0BI).
- OK
PowerSupplies.SchDoc
- The power distribution must be re-designed as follow:
- I used so many DC/DCs because there was requirement for stand-alone operation from 12V
- Use 3.3V from VME.
- OK
- Use one TPS52126 DC/DC to generate 1.2V and 2.5V from VME 5V.
- OK
- Use one TPS52126 DC/DC to generate 1.5V from VME 5V.
It can be placed close to the DDR chips as they're the only one using 1.5V
-> OR use three single DC/DC to generate 1.2V, 1.5V and 2.5V.
In any cases use the same DC/DC type to reduce the BOM.- I will use ones from SPEC since they work fine
- The VME 12V is only used for the FMC slot.
- OK
- Use a big Molex connector (c.f. for standard PC motherboard) to
provide 12V, 5V and 3.3V in stand-alone.
- OK, great idea
- LEDs on all voltage rails should be removed, only one LED to
indicate that the board is powered is enough.
-
well, here I can argue, LEDs don't cost much but after one look
U can se what is going on with the board
- One LED: simplicity, only used during debugging, lower cost anyway. Note that base cost is multiplied by a factor when a card is sold.
-
well, here I can argue, LEDs don't cost much but after one look
U can se what is going on with the board
- If possible, use only one inductor type.
-
it would cause higher ripples and would require more capacitors
when I insert everywhere 1uH
- Ripple will not be a problem. Simplicity. Add capacitance only when you think it is really necessary.
-
it would cause higher ripples and would require more capacitors
when I insert everywhere 1uH
- C24 and C41 are rated 6.3V but connected to 12V!!
- ups, my mistake
- If possible, use only one fuse type.
- see what I can do
USB.SchDoc
- Remove the FT2232 chip.
-
I will keep it for high speed stand-alone operation, all the
components will be marked as not mounted.
- Indeed, as was discussed in a separate mail: "only if it does not have any consequences for routing".
-
I will keep it for high speed stand-alone operation, all the
components will be marked as not mounted.
- Replace the CP2102 by a CP2103 and use the GPIO pins for the JTAG
emulation.
- hope that you have some libraries? For FTDI I use nice, open source libraries that emulate xilinx USB cable very well.
SFPGA.SchDoc
- The DIP switches can be removed. Not useful in a VME64x system.
-
how are U going to set the board address? Using just physical
one from the crate?
- Indeed, we use geographical adressing. The board cannot be used in standard VME as there is no 3.3V present.
- Anyway, we think now that some switch could be handy. Can you keep it on, but mark it as not-mounted. Wired to both FPGAs.
-
how are U going to set the board address? Using just physical
one from the crate?
- Move FMC I2C buses, FMC JTAG, FMC PGM2C, FMC Prsnt to AFPGA.
- OK
- Move temp. sensor and PCB revision resistor to AFPGA.
- OK
- Four or five PCB revision resistors are enough.
- OK
AFPGA_power.SchDoc
- Component for encription should be "not mounted" by default.
- OK
- 1nF decoupling capacitors should be removed.
-
did you try such option? In SPEC I used 10nF. I would affraid
to use only 100nF and 22uF for GTPs
- On SPEC there is 22uF, 1uF and 100nF for the GTP. So it does work. The power planes decouple too.
-
did you try such option? In SPEC I used 10nF. I would affraid
to use only 100nF and 22uF for GTPs
ClkGeneration.SchDoc
- Use the 20MHz VCXO for the SFPGA clock.
- since will be used for booting only, it is fine
- PLL_FMC2_2P2 and L_FPGA_CLK are sharing the same divider in the
AD9516. Is that correct?
-
depends for what U want to use it
- Good point and we discussed about it here. Can you replace this large PLL by two of the same type as used on the SPEC CDCM61004RHBT. Simplicity, same as SPEC, more independent clocks and can power down.
- Put the signals on current outputs 6-9 on one chip and those on 1-5 on another. Connect the CE of the chips to the AFPGA so that it can be powered down. The AFPGA always can run from another clock.
- Move the components connected to SFP_CLK to the SFP page and mark them as non-mounted.
-
depends for what U want to use it
- What is PLL_REF1 for?
-
I copied solution from VFC
- Likely can be removed. Please check. The signal would be missing a termination too.
-
I copied solution from VFC
FrontPannel.SchDoc
- Remove 51ohm serial termination resistors.
- Add MOSFET to enable the 50ohm parallel terminations.
If the LEMO is used as an output, we don't want is to be terminated at the source.- MOSFET controlled by the AFPGA
- Is this comment taken into account?
- MOSFET controlled by the AFPGA
Minor (Readability)
General
- OHR project is called SVEC, Altium project SVFC, top schematics VMEFMC.
- SVEC should be used everywhere to avoid confusion.
- Add the OHL license text on all sheets. Copy this text block from the SPEC schematics
- Use only A3 size for the schematics sheets. The 'top' sheet probably won't fit on an A3, so keep it A2.
- Use the same naming convention for the active low signals (#, _N, n, N). Notation with "_N" suffix is prefered.
- Sheet numbering is not up-to-date, several sheets have the same number.
- Use the same naming convention for the schematics files (e.g. all in lower case).
- The top level sheet should contain "top" in the file name.
- Avoid leaving big empty space on a sheet.
- OK
VMEFMC.SchDoc
- Add names on the blocks.
- Indentation of the comment block is screwed and makes it hard to read.
- Line crossing other blocks (P2_DATA).
- Group pins per inteface and add interface description on the block (as text).
- Consider using harness (e.g VME bus).
-
OK. I've heard that DEM doesn't like harnesses, project
versioning and other Altium features:)
- Never mind. Leave as is.
-
OK. I've heard that DEM doesn't like harnesses, project
versioning and other Altium features:)
JTAG&CONFIG.SchDoc
- The SFPGA boot mode is always "Master SPI", the comment should be
updated.
- OK
FmcConnector.SchDoc
- Remove "LVSD high speed" comments.
- Replace "LaP and LaN are LVSD lines" comments by something more generic, like "LaP and LaN are 100ohms diff. pairs".
- Add "FMC Slot 1" and "FMC Slot 2" comments.
- OK
VmeConnector.SchDoc
- "LVDS pairs" comment should be more generic, like "100ohms diff. pairs".
- Use arrow symbol for voltage rails (as on PowerSupplies sheet).
- Change V12P0VME to P12V_VME.
- Change V12N0VME to M12V_VME.
- Change V5P0VME to P5V_VME.
- Change V5P0STDBYVME to P5V_STDBY_VME.
- Add "_N" to active low signals.
- OK
DDR3.SchDoc
- DDR_CAS and DDR_RAS are active low signals, add "_N".
- OK
DDR3_2.SchDoc
- DDR_2_CAS and DDR_2_RAS are active low signals, add "_N".
- OK
AFPGA.SchDoc
- Add bank supply voltage as a comment next to each block.
- Some port symbols are too small.
- Uniformise the net names (e.g. all in upper case).
- OK
fpga_gtp.SchDoc
- The sheet template doesn't fit the sheet size, the title block is in
the middle of the page.
- OK, I've mentioned that already
USB.SchDoc
- The sheet template doesn't fit the sheet size, the title block is in
the middle of the page.
- OK, I've mentioned that already
SFPGA.SchDoc
- Add bank supply voltage as a comment next to each block.
- OK