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TDC core
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084b8b22
Commit
084b8b22
authored
Aug 28, 2011
by
Sebastien Bourdeauducq
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lbc: enable retiming
parent
814967a3
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core/tdc_lbc.vhd
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084b8b22
...
@@ -82,6 +82,12 @@ signal polarity_d1 : std_logic;
...
@@ -82,6 +82,12 @@ signal polarity_d1 : std_logic;
signal
polarity_d2
:
std_logic
;
signal
polarity_d2
:
std_logic
;
signal
count_reg
:
std_logic_vector
(
g_N
-1
downto
0
);
signal
count_reg
:
std_logic_vector
(
g_N
-1
downto
0
);
signal
d_completed
:
std_logic_vector
(
2
**
g_N
-2
downto
0
);
signal
d_completed
:
std_logic_vector
(
2
**
g_N
-2
downto
0
);
-- enable retiming
attribute
register_balancing
:
string
;
attribute
register_balancing
of
count_reg
:
signal
is
"backward"
;
attribute
register_balancing
of
count_o
:
signal
is
"backward"
;
begin
begin
g_expand
:
if
g_NIN
<
2
**
g_N
-1
generate
g_expand
:
if
g_NIN
<
2
**
g_N
-1
generate
d_completed
<=
d_i
&
(
2
**
g_N
-1
-
g_NIN
-1
downto
0
=>
not
polarity
);
d_completed
<=
d_i
&
(
2
**
g_N
-1
-
g_NIN
-1
downto
0
=>
not
polarity
);
...
...
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