lbc: register output

parent 3d934c48
......@@ -27,6 +27,7 @@ entity tdc_lbc is
g_N : positive
);
port (
clk_i : in std_logic;
polarity_i : in std_logic;
d_i : in std_logic_vector(2**g_N-2 downto 0);
count_o : out std_logic_vector(g_N-1 downto 0)
......@@ -70,5 +71,10 @@ end function;
signal d_x : std_logic_vector(d_i'length-1 downto 0);
begin
d_x <= (d_i'length-1 downto 0 => polarity_i) xor d_i;
count_o <= f_clo(d_x);
process(clk_i)
begin
if rising_edge(clk_i) then
count_o <= f_clo(d_x);
end if;
end process;
end architecture;
......@@ -59,6 +59,7 @@ begin
return result;
end function;
signal clk : std_logic;
signal polarity : std_logic;
signal d : std_logic_vector(2**g_N-2 downto 0);
signal count : std_logic_vector(g_N-1 downto 0);
......@@ -69,6 +70,7 @@ begin
g_N => g_N
)
port map(
clk_i => clk,
polarity_i => polarity,
d_i => d,
count_o => count
......@@ -96,7 +98,10 @@ begin
end if;
end loop;
-- generate, print and verify output
wait for 10 ns;
clk <= '0';
wait for 4 ns;
clk <= '1';
wait for 4 ns;
report "Vector:" & str(d) & " Expected:" & integer'image(i) & " Result:" & integer'image(to_integer(unsigned(count)));
assert i = to_integer(unsigned(count)) severity failure;
end loop;
......
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