Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
T
TDC core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
TDC core
Commits
0ed26a85
Commit
0ed26a85
authored
Oct 22, 2011
by
Sebastien Bourdeauducq
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
demo: add header file for TDC
parent
836ecfde
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
407 additions
and
0 deletions
+407
-0
tdc.h
demo/software/include/hw/tdc.h
+407
-0
No files found.
demo/software/include/hw/tdc.h
0 → 100644
View file @
0ed26a85
/*
Register definitions for slave core: TDC
* File : tdc.h
* Author : auto-generated by wbgen2 from hostif.wb
* Created : Fri Oct 21 22:26:32 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE hostif.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_HOSTIF_WB
#define __WBGEN2_REGDEFS_HOSTIF_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control and status */
/* definitions for field: Reset in reg: Control and status */
#define TDC_CS_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Ready in reg: Control and status */
#define TDC_CS_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Deskew value for channel 0 (high word) */
/* definitions for register: Deskew value for channel 0 (low word) */
/* definitions for register: Deskew value for channel 1 (high word) */
/* definitions for register: Deskew value for channel 1 (low word) */
/* definitions for register: Deskew value for channel 2 (high word) */
/* definitions for register: Deskew value for channel 2 (low word) */
/* definitions for register: Deskew value for channel 3 (high word) */
/* definitions for register: Deskew value for channel 3 (low word) */
/* definitions for register: Deskew value for channel 4 (high word) */
/* definitions for register: Deskew value for channel 4 (low word) */
/* definitions for register: Deskew value for channel 5 (high word) */
/* definitions for register: Deskew value for channel 5 (low word) */
/* definitions for register: Deskew value for channel 6 (high word) */
/* definitions for register: Deskew value for channel 6 (low word) */
/* definitions for register: Deskew value for channel 7 (high word) */
/* definitions for register: Deskew value for channel 7 (low word) */
/* definitions for register: Detected polarities */
/* definitions for register: Raw measured value for channel 0 */
/* definitions for register: Fixed point measurement for channel 0 (high word) */
/* definitions for register: Fixed point measurement for channel 0 (low word) */
/* definitions for register: Raw measured value for channel 1 */
/* definitions for register: Fixed point measurement for channel 1 (high word) */
/* definitions for register: Fixed point measurement for channel 1 (low word) */
/* definitions for register: Raw measured value for channel 2 */
/* definitions for register: Fixed point measurement for channel 2 (high word) */
/* definitions for register: Fixed point measurement for channel 2 (low word) */
/* definitions for register: Raw measured value for channel 3 */
/* definitions for register: Fixed point measurement for channel 3 (high word) */
/* definitions for register: Fixed point measurement for channel 3 (low word) */
/* definitions for register: Raw measured value for channel 4 */
/* definitions for register: Fixed point measurement for channel 4 (high word) */
/* definitions for register: Fixed point measurement for channel 4 (low word) */
/* definitions for register: Raw measured value for channel 5 */
/* definitions for register: Fixed point measurement for channel 5 (high word) */
/* definitions for register: Fixed point measurement for channel 5 (low word) */
/* definitions for register: Raw measured value for channel 6 */
/* definitions for register: Fixed point measurement for channel 6 (high word) */
/* definitions for register: Fixed point measurement for channel 6 (low word) */
/* definitions for register: Raw measured value for channel 7 */
/* definitions for register: Fixed point measurement for channel 7 (high word) */
/* definitions for register: Fixed point measurement for channel 7 (low word) */
/* definitions for register: Debug control */
/* definitions for field: Freeze request in reg: Debug control */
#define TDC_DCTL_REQ WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Freeze acknowledgement in reg: Debug control */
#define TDC_DCTL_ACK WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Channel selection */
/* definitions for field: Switch to next channel in reg: Channel selection */
#define TDC_CSEL_NEXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Last channel reached in reg: Channel selection */
#define TDC_CSEL_LAST WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Calibration signal selection */
/* definitions for register: LUT read address */
/* definitions for register: LUT read data */
/* definitions for register: Histogram read address */
/* definitions for register: Histogram read data */
/* definitions for register: Frequency counter control and status */
/* definitions for field: Measurement start in reg: Frequency counter control and status */
#define TDC_FCC_ST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Measurement ready in reg: Frequency counter control and status */
#define TDC_FCC_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Frequency counter current value */
/* definitions for register: Frequency counter stored value */
/* definitions for register: Interrupt disable register */
/* definitions for field: Event detection 0 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Event detection 1 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Event detection 2 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Event detection 3 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Event detection 4 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Event detection 5 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Event detection 6 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Event detection 7 in reg: Interrupt disable register */
#define TDC_EIC_IDR_IE7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Startup calibration done in reg: Interrupt disable register */
#define TDC_EIC_IDR_ISC WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Coarse counter overflow in reg: Interrupt disable register */
#define TDC_EIC_IDR_ICC WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Event detection 0 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Event detection 1 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Event detection 2 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Event detection 3 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Event detection 4 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Event detection 5 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Event detection 6 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Event detection 7 in reg: Interrupt enable register */
#define TDC_EIC_IER_IE7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Startup calibration done in reg: Interrupt enable register */
#define TDC_EIC_IER_ISC WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Coarse counter overflow in reg: Interrupt enable register */
#define TDC_EIC_IER_ICC WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Event detection 0 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Event detection 1 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Event detection 2 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Event detection 3 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Event detection 4 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Event detection 5 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Event detection 6 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Event detection 7 in reg: Interrupt mask register */
#define TDC_EIC_IMR_IE7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Startup calibration done in reg: Interrupt mask register */
#define TDC_EIC_IMR_ISC WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Coarse counter overflow in reg: Interrupt mask register */
#define TDC_EIC_IMR_ICC WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Event detection 0 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Event detection 1 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Event detection 2 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Event detection 3 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Event detection 4 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Event detection 5 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Event detection 6 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Event detection 7 in reg: Interrupt status register */
#define TDC_EIC_ISR_IE7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Startup calibration done in reg: Interrupt status register */
#define TDC_EIC_ISR_ISC WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Coarse counter overflow in reg: Interrupt status register */
#define TDC_EIC_ISR_ICC WBGEN2_GEN_MASK(9, 1)
PACKED
struct
TDC_WB
{
/* [0x0]: REG Control and status */
uint32_t
CS
;
/* [0x4]: REG Deskew value for channel 0 (high word) */
uint32_t
DESH0
;
/* [0x8]: REG Deskew value for channel 0 (low word) */
uint32_t
DESL0
;
/* [0xc]: REG Deskew value for channel 1 (high word) */
uint32_t
DESH1
;
/* [0x10]: REG Deskew value for channel 1 (low word) */
uint32_t
DESL1
;
/* [0x14]: REG Deskew value for channel 2 (high word) */
uint32_t
DESH2
;
/* [0x18]: REG Deskew value for channel 2 (low word) */
uint32_t
DESL2
;
/* [0x1c]: REG Deskew value for channel 3 (high word) */
uint32_t
DESH3
;
/* [0x20]: REG Deskew value for channel 3 (low word) */
uint32_t
DESL3
;
/* [0x24]: REG Deskew value for channel 4 (high word) */
uint32_t
DESH4
;
/* [0x28]: REG Deskew value for channel 4 (low word) */
uint32_t
DESL4
;
/* [0x2c]: REG Deskew value for channel 5 (high word) */
uint32_t
DESH5
;
/* [0x30]: REG Deskew value for channel 5 (low word) */
uint32_t
DESL5
;
/* [0x34]: REG Deskew value for channel 6 (high word) */
uint32_t
DESH6
;
/* [0x38]: REG Deskew value for channel 6 (low word) */
uint32_t
DESL6
;
/* [0x3c]: REG Deskew value for channel 7 (high word) */
uint32_t
DESH7
;
/* [0x40]: REG Deskew value for channel 7 (low word) */
uint32_t
DESL7
;
/* [0x44]: REG Detected polarities */
uint32_t
POL
;
/* [0x48]: REG Raw measured value for channel 0 */
uint32_t
RAW0
;
/* [0x4c]: REG Fixed point measurement for channel 0 (high word) */
uint32_t
MESH0
;
/* [0x50]: REG Fixed point measurement for channel 0 (low word) */
uint32_t
MESL0
;
/* [0x54]: REG Raw measured value for channel 1 */
uint32_t
RAW1
;
/* [0x58]: REG Fixed point measurement for channel 1 (high word) */
uint32_t
MESH1
;
/* [0x5c]: REG Fixed point measurement for channel 1 (low word) */
uint32_t
MESL1
;
/* [0x60]: REG Raw measured value for channel 2 */
uint32_t
RAW2
;
/* [0x64]: REG Fixed point measurement for channel 2 (high word) */
uint32_t
MESH2
;
/* [0x68]: REG Fixed point measurement for channel 2 (low word) */
uint32_t
MESL2
;
/* [0x6c]: REG Raw measured value for channel 3 */
uint32_t
RAW3
;
/* [0x70]: REG Fixed point measurement for channel 3 (high word) */
uint32_t
MESH3
;
/* [0x74]: REG Fixed point measurement for channel 3 (low word) */
uint32_t
MESL3
;
/* [0x78]: REG Raw measured value for channel 4 */
uint32_t
RAW4
;
/* [0x7c]: REG Fixed point measurement for channel 4 (high word) */
uint32_t
MESH4
;
/* [0x80]: REG Fixed point measurement for channel 4 (low word) */
uint32_t
MESL4
;
/* [0x84]: REG Raw measured value for channel 5 */
uint32_t
RAW5
;
/* [0x88]: REG Fixed point measurement for channel 5 (high word) */
uint32_t
MESH5
;
/* [0x8c]: REG Fixed point measurement for channel 5 (low word) */
uint32_t
MESL5
;
/* [0x90]: REG Raw measured value for channel 6 */
uint32_t
RAW6
;
/* [0x94]: REG Fixed point measurement for channel 6 (high word) */
uint32_t
MESH6
;
/* [0x98]: REG Fixed point measurement for channel 6 (low word) */
uint32_t
MESL6
;
/* [0x9c]: REG Raw measured value for channel 7 */
uint32_t
RAW7
;
/* [0xa0]: REG Fixed point measurement for channel 7 (high word) */
uint32_t
MESH7
;
/* [0xa4]: REG Fixed point measurement for channel 7 (low word) */
uint32_t
MESL7
;
/* [0xa8]: REG Debug control */
uint32_t
DCTL
;
/* [0xac]: REG Channel selection */
uint32_t
CSEL
;
/* [0xb0]: REG Calibration signal selection */
uint32_t
CAL
;
/* [0xb4]: REG LUT read address */
uint32_t
LUTA
;
/* [0xb8]: REG LUT read data */
uint32_t
LUTD
;
/* [0xbc]: REG Histogram read address */
uint32_t
HISA
;
/* [0xc0]: REG Histogram read data */
uint32_t
HISD
;
/* [0xc4]: REG Frequency counter control and status */
uint32_t
FCC
;
/* [0xc8]: REG Frequency counter current value */
uint32_t
FCR
;
/* [0xcc]: REG Frequency counter stored value */
uint32_t
FCSR
;
/* padding to: 56 words */
uint32_t
__padding_0
[
4
];
/* [0xe0]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0xe4]: REG Interrupt enable register */
uint32_t
EIC_IER
;
/* [0xe8]: REG Interrupt mask register */
uint32_t
EIC_IMR
;
/* [0xec]: REG Interrupt status register */
uint32_t
EIC_ISR
;
};
#endif
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment