hostif: fix VHDL problems

parent b4ea135f
......@@ -354,14 +354,14 @@ begin
-- end autogenerated connections
);
-- All synthesizers I know of will set unconnected bits to 0.
lut_a <= wbg_luta(g_RAW_COUNT-1 downto 0);
wbg_lutd <= (others => '0', lut_d);
wbg_lutd(lut_d'range) <= lut_d;
his_a <= wbg_hisa(g_RAW_COUNT-1 downto 0);
wbg_hisd <= (others => '0', his_d);
wbg_fcr <= (others => '0', oc_freq);
wbg_fcsr <= (others => '0', oc_sfreq);
wbg_hisd(his_d'range) <= his_d;
wbg_fcr(oc_freq'range) <= oc_freq;
wbg_fcsr(oc_sfreq'range) <= oc_sfreq;
-- All synthesizers I know of will set unconnected bits to 0.
g_connect: for i in 0 to g_CHANNEL_COUNT-1 generate
deskew((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT))
<= wbg_des(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64);
......@@ -370,7 +370,7 @@ begin
wbg_mes(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64)
<= fp((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT));
end generate;
wbg_pol <= (others => '0', polarity);
wbg_ie <= (others => '0', detect);
wbg_pol(polarity'range) <= polarity;
wbg_ie(detect'range) <= detect;
end architecture;
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