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TDC core
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3d934c48
Commit
3d934c48
authored
Aug 03, 2011
by
Sebastien Bourdeauducq
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Prefix variables with v
parent
6af2b4a1
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tb_lbc.vhd
tb/lbc/tb_lbc.vhd
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tb/lbc/tb_lbc.vhd
View file @
3d934c48
...
...
@@ -31,20 +31,20 @@ end entity;
architecture
tb
of
tb_lbc
is
function
chr
(
sl
:
std_logic
)
return
character
is
variable
c
:
character
;
variable
v_
c
:
character
;
begin
case
sl
is
when
'U'
=>
c
:
=
'U'
;
when
'X'
=>
c
:
=
'X'
;
when
'0'
=>
c
:
=
'0'
;
when
'1'
=>
c
:
=
'1'
;
when
'Z'
=>
c
:
=
'Z'
;
when
'W'
=>
c
:
=
'W'
;
when
'L'
=>
c
:
=
'L'
;
when
'H'
=>
c
:
=
'H'
;
when
'-'
=>
c
:
=
'-'
;
when
'U'
=>
v_
c
:
=
'U'
;
when
'X'
=>
v_
c
:
=
'X'
;
when
'0'
=>
v_
c
:
=
'0'
;
when
'1'
=>
v_
c
:
=
'1'
;
when
'Z'
=>
v_
c
:
=
'Z'
;
when
'W'
=>
v_
c
:
=
'W'
;
when
'L'
=>
v_
c
:
=
'L'
;
when
'H'
=>
v_
c
:
=
'H'
;
when
'-'
=>
v_
c
:
=
'-'
;
end
case
;
return
c
;
return
v_
c
;
end
function
;
function
str
(
slv
:
std_logic_vector
)
return
string
is
...
...
@@ -75,11 +75,11 @@ begin
);
polarity
<=
'0'
;
process
variable
seed1
:
positive
:
=
1
;
variable
seed2
:
positive
:
=
2
;
variable
rand
:
real
;
variable
int_rand
:
integer
;
variable
stim
:
std_logic_vector
(
0
downto
0
);
variable
v_
seed1
:
positive
:
=
1
;
variable
v_
seed2
:
positive
:
=
2
;
variable
v_
rand
:
real
;
variable
v_
int_rand
:
integer
;
variable
v_
stim
:
std_logic_vector
(
0
downto
0
);
begin
for
i
in
0
to
2
**
g_N
-1
loop
-- generate test vector
...
...
@@ -89,10 +89,10 @@ begin
elsif
j
=
2
**
g_N
-2
-
i
then
d
(
j
)
<=
'0'
;
else
uniform
(
seed1
,
seed2
,
rand
);
int_rand
:
=
integer
(
trunc
(
rand
*
2
.
0
));
stim
:
=
std_logic_vector
(
to_unsigned
(
int_rand
,
stim
'length
));
d
(
j
)
<=
stim
(
0
);
uniform
(
v_seed1
,
v_seed2
,
v_
rand
);
v_int_rand
:
=
integer
(
trunc
(
v_
rand
*
2
.
0
));
v_stim
:
=
std_logic_vector
(
to_unsigned
(
v_int_rand
,
v_
stim
'length
));
d
(
j
)
<=
v_
stim
(
0
);
end
if
;
end
loop
;
-- generate, print and verify output
...
...
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