doc: demonstration design

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\usepackage{url} \usepackage{url}
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\maketitle{} \maketitle{}
\section{The demonstration design} \section{The demonstration design}
\subsection{Hardware} \subsection{Hardware}
The demonstration design runs on a SPEC board equipped with a FMC DIO 5-channel daughterboard.
Data is transferred at 115200 8-N-1 via the serial console accessible using the built-in USB adapter. The PCIe interface is not used.
Test signals go through the FMC daughterboard. The first LEMO connector on the daughterboard is configured as output and transmits an oscillating pattern. The next two LEMO connectors are inputs connected to TDC channels.
For measuring the FPGA temperature, the 1-wire sensor IC19 is placed on top of the FPGA using kapton tape. Thermal paste improves conduction between the FPGA and the sensor.
\subsection{Contents} \subsection{Contents}
The demonstration design contains:
\begin{itemize}
\item the LatticeMico32 soft processor, running at 125MHz from the clock generated by the CDCM61004 chip on the SPEC.
\item UART, timer and GPIO cores from the Milkymist SoC. Memory-mapped.
\item the TDC core with its Wishbone interface, configured for two channels, also clocked from the 125MHz source. Memory-mapped.
\item a ring oscillator for startup calibration of the TDC core.
\item an oscillator for generating TDC test signals.
\item a basic boot ROM and command line interface based on the Milkymist BIOS.
\item software routines for testing the TDC core.
\end{itemize}
\subsection{TDC core implementation details} \subsection{TDC core implementation details}
The TDC core is implemented with the following parameters:
\begin{figure}[!h]
\begin{center}
\begin{tabular}{|l|c|}
\hline
g\_CHANNEL\_COUNT & 2 \\
\hline
g\_CARRY4\_COUNT & 124 \\
\hline
g\_RAW\_COUNT & 9 \\
\hline
g\_FP\_COUNT & 13 \\
\hline
g\_EXHIS\_COUNT & 5 \\
\hline
g\_COARSE\_COUNT & 25 \\
\hline
g\_RO\_LENGTH & 31 \\
\hline
g\_FCOUNTER\_WIDTH & 13 \\
\hline
g\_FTIMER\_WIDTH & 14 \\
\hline
\end{tabular}
\end{center}
To minimize variations of the timing properties between runs of the automated place and route tool and to maximize thermal coupling between each delay line and its online calibration oscillator, the design is floorplanned.
The two delay lines from each channel are placed close to their respective IOBs. Because of their large height, there are few FPGA columns that can accomodate them, and they accidentally ended up close to each other. The ring oscillator components are placed in the SLICEX columns just at the right of the delay lines, and spread evenly along the height of the delay line. This is illustrated by Figure \ref{fig:floorplan}, where the delay line is colored in pink and the ring oscillator is yellow.
In the UCF file, this is achieved by manually placing the first CARRY4 primitive in each delay line. Since carry chains can only be placed in columns, this determines the placement for the complete delay line. For the ring oscillators, a Python script generates one placement constraint for each element.
\begin{figure}[h]
\centering \centering
\includegraphics[width=1.6cm]{floorplan.png} \includegraphics[width=1.6cm]{floorplan.png}
\caption{Floorplan of the delay lines and ring oscillators in FPGA Editor.} \caption{Floorplan of the delay lines and ring oscillators in FPGA Editor.}
\label{fig:floorplan} \label{fig:floorplan}
\end{figure} \end{figure}
\begin{figure}[!h] In the input signal path, there are one multiplexer and one inverter per channel. Everything is packed into one FPGA slice, which is also manually placed to minimize timing variations. The physical input signal path can be seen in Figure \ref{fig:inputpath}. The LVDS IOBs are represented in blue, and the routing and the slice in green.
\begin{figure}[h]
\includegraphics[width=\textwidth]{input_routes.png} \includegraphics[width=\textwidth]{input_routes.png}
\caption{Input signal path in FPGA Editor.} \caption{Input signal path in FPGA Editor.}
\label{fig:inputpath} \label{fig:inputpath}
\end{figure} \end{figure}
\subsection{Synthesizing and running the design} \subsection{Synthesizing and running the design}
\subsubsection{Compiling the LM32 software}
Since the LM32 software is used in block RAM initialization, it must be compiled before the FPGA bitstream is built. The scripts expect the lm32-rtems4.11 GCC toolchain, but any LM32 toolchain should be suitable.
You will need first to compile some host tools which are used to build block RAM initialization files:
\begin{verbatim}
cd $TDCDIR/demo/tools
make
\end{verbatim}
Then, compile the base library and the software image:
\begin{verbatim}
cd $TDCDIR/demo/software/libbase
make
cd $TDCDIR/demo/software/demo
make
\end{verbatim}
\subsubsection{Compiling the FPGA bitstream}
The design can be synthesized with ISE 13.2. You will also need Python to generate the floorplanning constraints. The compilation is automatic:
\begin{verbatim}
cd $TDCDIR/demo/boards/spec/synthesis
make -f Makefile.xst
\end{verbatim}
\subsubsection{Downloading the FPGA bitstream}
If you are using Xilinx iMPACT, there is an automatic script:
\begin{verbatim}
cd $TDCDIR/demo/boards/spec/synthesis
make -f Makefile.xst load
\end{verbatim}
Otherwise, load the file \verb!$TDCDIR/demo/boards/spec/synthesis/build/system.bit! with your favorite FPGA programming tool.
\subsection{Command line interface} \subsection{Command line interface}
Once the bitstream is loaded, it implements a command-line interface on the serial console (115200 8-N-1), and it displays a \textbf{TDC>} prompt. From there, you can enter the following commands:
\section{Method and results}
\begin{tabularx}{\textwidth}{|l|X|}
\hline
mr <address> [length] & Reads memory. Length is in bytes (default 1). \\
\hline
mw <address> <value> [count] & Writes one or several 32-bit words to memory. Count is in words (default 1). \\
\hline
temp & Displays the current temperature in \degree C measured by the 1-wire sensor. \\
\hline
rofreq & Outputs a series of comma-separated values representing the current temperature (in \degree C) and the ring oscillator frequencies (measured in counts) from each TDC channel. Sending any character to the console stops the series of measurements. \\
\hline
calinfo & Dumps the current contents of the histogram and the LUT for each TDC channel. \\
\hline
daclevel <value> & Sets the output voltage on all channels of the I2C DAC5578 digital to analog converter on the FMC DIO board. The 16-bit value is directly written into the DAC. \\
\hline
mraw & Outputs a series of raw (pre-LUT) measurements from the first TDC channel. Sending any character to the console stops the series of measurements. \\
\hline
diff & In a loop, waits for a TDC event to happen in both channels, and displays its parameters. The output is in CSV format and contains the following information: polarity for the first channel, raw timestamp for the first channel, fixed-point timestamp for the first channel, and the same for the second channel. Sending any character to the console stops the series of measurements. \\
\hline
\end{tabularx}
\section{Methods and results}
\subsection{Temperature measurement with ring oscillators} \subsection{Temperature measurement with ring oscillators}
\label{sec:rofreq} \label{sec:rofreq}
\begin{figure}[!h] \begin{figure}[h]
\includegraphics[width=\textwidth]{rofreq.pdf} \includegraphics[width=\textwidth]{rofreq.pdf}
\caption{Dependence of ring oscillator frequencies on temperature.} \caption{Dependence of ring oscillator frequencies on temperature.}
\label{fig:rofreq} \label{fig:rofreq}
\end{figure} \end{figure}
\subsection{Startup calibration stability} \subsection{Startup calibration stability}
Temperature is 37C. Temperature is 37\degree C.
\begin{figure}[!h] \begin{figure}[h]
\includegraphics[width=\textwidth]{scs.pdf} \includegraphics[width=\textwidth]{scs.pdf}
\caption{Difference between the LUT contents from two startup calibrations at the same temperature.} \caption{Difference between the LUT contents from two startup calibrations at the same temperature.}
\label{fig:scs} \label{fig:scs}
...@@ -69,7 +173,7 @@ Temperature is 37C. ...@@ -69,7 +173,7 @@ Temperature is 37C.
\subsection{Differential TDC} \subsection{Differential TDC}
Temperature is 36.9375\degree C Temperature is 36.9375\degree C
\begin{figure}[!h] \begin{figure}[h]
\includegraphics[width=\textwidth]{mhist.pdf} \includegraphics[width=\textwidth]{mhist.pdf}
\caption{Differential measurements} \caption{Differential measurements}
\label{fig:mhistll} \label{fig:mhistll}
...@@ -80,13 +184,13 @@ Even though the influence of temperature is small (\ref{sec:rofreq}), we can sti ...@@ -80,13 +184,13 @@ Even though the influence of temperature is small (\ref{sec:rofreq}), we can sti
We brought the temperature to from 37\degree C to 47.875\degree C, and ran startup calibration again. We observed a significant difference between the LUT contents (figure \ref{fig:chtmlt}). We brought the temperature to from 37\degree C to 47.875\degree C, and ran startup calibration again. We observed a significant difference between the LUT contents (figure \ref{fig:chtmlt}).
\begin{figure}[!h] \begin{figure}[h]
\includegraphics[width=\textwidth]{chtmlt.pdf} \includegraphics[width=\textwidth]{chtmlt.pdf}
\caption{Difference between the LUT contents from two startup calibrations at high and low temperatures.} \caption{Difference between the LUT contents from two startup calibrations at high and low temperatures.}
\label{fig:chtmlt} \label{fig:chtmlt}
\end{figure} \end{figure}
\begin{figure}[!h] \begin{figure}[h]
\includegraphics[width=\textwidth]{chtmht.pdf} \includegraphics[width=\textwidth]{chtmht.pdf}
\caption{Difference between the LUT contents from startup calibration and the values computed by online calibration.} \caption{Difference between the LUT contents from startup calibration and the values computed by online calibration.}
\label{fig:chtmht} \label{fig:chtmht}
......
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