demo: floorplan ring oscillators

parent 4d250b87
......@@ -10,8 +10,9 @@ SRC_VHDL=$(CORES_SRC_VHDL)
all: build/system.bit
build/system.ucf: common.ucf xst.ucf
build/system.ucf: common.ucf xst.ucf floorplan_oscillators.py
cat common.ucf xst.ucf > build/system.ucf
./floorplan_oscillators.py >> build/system.ucf
build/system.prj: $(SRC) $(SRC_VHDL)
rm -f build/system.prj
......
#!/usr/bin/python
print "# ==== Autogenerated startup calibration oscillator floorplan ===="
for channel in range(0,2):
for lut in range(0,31):
target_slice_x = 31 + 2*channel
target_slice_y = lut*123//30 + 2
if lut == 0:
gen = "g_firstlut"
else:
gen = "g_nextlut"
print \
"INST " \
"\"tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[%d].cmp_channel/cmp_ringosc/g_luts[%d].%s.cmp_LUT\"" \
" LOC = SLICE_X%dY%d;" \
% (channel, lut, gen, target_slice_x, target_slice_y)
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