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TDC core
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TDC core
Commits
96fd461c
Commit
96fd461c
authored
Oct 25, 2011
by
Sebastien Bourdeauducq
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hostif: regenerate wbgen file
parent
2ee3da6c
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15 additions
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3 deletions
+15
-3
tdc_wb.vhd
hostif/tdc_wb.vhd
+15
-3
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hostif/tdc_wb.vhd
View file @
96fd461c
...
...
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_wb.vhd
-- Author : auto-generated by wbgen2 from tdc
_wb
.wb
-- Created :
Sat Aug 27 17:26:44
2011
-- Author : auto-generated by wbgen2 from tdc.wb
-- Created :
Tue Oct 25 16:54:19
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc
_wb
.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -267,7 +267,10 @@ begin
when
"000000"
=>
if
(
wb_we_i
=
'1'
)
then
tdc_cs_rst_int
<=
wrdata_reg
(
0
);
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
tdc_cs_rdy_i
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
...
...
@@ -631,7 +634,9 @@ begin
ack_in_progress
<=
'1'
;
when
"101010"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
tdc_dctl_req_int
<=
wrdata_reg
(
0
);
rddata_reg
(
1
)
<=
'X'
;
else
rddata_reg
(
0
)
<=
tdc_dctl_req_int
;
rddata_reg
(
1
)
<=
tdc_dctl_ack_i
;
...
...
@@ -671,7 +676,10 @@ begin
when
"101011"
=>
if
(
wb_we_i
=
'1'
)
then
tdc_csel_next_int
<=
wrdata_reg
(
0
);
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
tdc_csel_last_i
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
...
...
@@ -708,6 +716,7 @@ begin
ack_in_progress
<=
'1'
;
when
"101100"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
tdc_cal_int
<=
wrdata_reg
(
0
);
else
rddata_reg
(
0
)
<=
tdc_cal_int
;
...
...
@@ -810,7 +819,10 @@ begin
when
"110001"
=>
if
(
wb_we_i
=
'1'
)
then
tdc_fcc_st_int
<=
wrdata_reg
(
0
);
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
tdc_fcc_rdy_i
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
...
...
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