Divider test bench

parent 530eddf4
......@@ -59,10 +59,11 @@ signal diff : std_logic_vector(g_WIDTH downto 0);
signal ready : std_logic;
begin
quotient_o <= qr(2*g_WIDTH-1 downto g_WIDTH);
remainder_o <= qr(g_WIDTH-1 downto 0);
quotient_o <= qr(g_WIDTH-1 downto 0);
remainder_o <= qr(2*g_WIDTH-1 downto g_WIDTH);
ready <= '1' when (counter = (counter'range => '0')) else '0';
ready_o <= ready;
diff <= std_logic_vector(unsigned(qr(2*g_WIDTH-1 downto g_WIDTH-1))
- unsigned("0" & divisor_r));
......@@ -76,13 +77,14 @@ begin
else
if start_i = '1' then
counter <= std_logic_vector(to_unsigned(g_WIDTH, counter'length));
qr <= (g_WIDTH-1 downto 0 => '0') & dividend;
divisor_r <= divisor;
qr <= (g_WIDTH-1 downto 0 => '0') & dividend_i;
divisor_r <= divisor_i;
elsif ready = '0' then
if diff(g_WIDTH) = '1' then
qr <= qr(2*g_WIDTH-2 downto 0) & "0";
else
qr <= diff(g_WIDTH-1 downto 0) & qr(g_WIDTH-2 downto 0) & "1";
end if;
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end if;
......
......@@ -152,6 +152,24 @@ component tdc_delayline is
);
end component;
component tdc_divider is
generic(
g_WIDTH: positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
start_i : in std_logic;
dividend_i : in std_logic_vector(g_WIDTH-1 downto 0);
divisor_i : in std_logic_vector(g_WIDTH-1 downto 0);
ready_o : out std_logic;
quotient_o : out std_logic_vector(g_WIDTH-1 downto 0);
remainder_o : out std_logic_vector(g_WIDTH-1 downto 0)
);
end component;
component tdc_psync is
port(
clk_src_i : in std_logic;
......
#!/bin/sh
set -e
ghdl -i ../../core/tdc_package.vhd ../../core/tdc_divider.vhd tb_divider.vhd
ghdl -m tb_divider
ghdl -r tb_divider
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tb_freqc
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Test bench for the integer divider
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-08-18 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 Sebastien Bourdeauducq
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
entity tb_divider is
generic(
g_WIDTH : positive := 5
);
end entity;
architecture tb of tb_divider is
signal clk : std_logic;
signal reset : std_logic;
signal start : std_logic;
signal dividend : std_logic_vector(g_WIDTH-1 downto 0);
signal divisor : std_logic_vector(g_WIDTH-1 downto 0);
signal ready : std_logic;
signal quotient : std_logic_vector(g_WIDTH-1 downto 0);
signal remainder : std_logic_vector(g_WIDTH-1 downto 0);
signal end_simulation : boolean := false;
begin
cmp_dut: tdc_divider
generic map(
g_WIDTH => g_WIDTH
)
port map(
clk_i => clk,
reset_i => reset,
start_i => start,
dividend_i => dividend,
divisor_i => divisor,
ready_o => ready,
quotient_o => quotient,
remainder_o => remainder
);
process
begin
clk <= '0';
wait for 4 ns;
clk <= '1';
wait for 4 ns;
if end_simulation then
wait;
end if;
end process;
process
variable v_quotient_got : integer;
variable v_remainder_got : integer;
variable v_quotient_exp : integer;
variable v_remainder_exp : integer;
begin
start <= '0';
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait until rising_edge(clk);
for p in 0 to 2**g_WIDTH-1 loop
for q in 1 to 2**g_WIDTH-1 loop
dividend <= std_logic_vector(to_unsigned(p, g_WIDTH));
divisor <= std_logic_vector(to_unsigned(q, g_WIDTH));
start <= '1';
wait until rising_edge(clk);
wait for 1 ns;
assert ready = '0' severity failure;
start <= '0';
wait until ready = '1';
v_quotient_got := to_integer(unsigned(quotient));
v_remainder_got := to_integer(unsigned(remainder));
v_quotient_exp := p/q;
v_remainder_exp := p rem q;
report integer'image(p) & " = " & integer'image(q)
& " * " & integer'image(v_quotient_got) & " + " & integer'image(v_remainder_got);
assert v_quotient_got = v_quotient_exp severity failure;
assert v_remainder_got = v_remainder_exp severity failure;
end loop;
end loop;
report "Test passed.";
end_simulation <= true;
wait;
end process;
end architecture;
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