Project description
The TDC core is a high precision (sub-nanosecond) time to digital conversion core for Xilinx Spartan-6 FPGAs.
Specifications
- Expected precision: 50-100ps.
- Typical range: 200ms (using a 32-bit value and 50ps steps).
- Latency: 4 to 6 cycles (not including host interface module).
- Uses a counter for coarse timing and a calibrated delay line for fine timing.
- Range: number of counter bits configurable with a VHDL generic.
- Delay line implemented with carry chain (CARRY4) primitives.
- Histogram booking and calibration as explained in the Fermilab paper.
- "Wave union" not implemented.
- Output signals (without host interface module):
- Periodic counter overflow.
- Received pulse notification (with counter value + fine timing).
- Optional host/CPU interface module:
- Wishbone slave.
- Configuration and status registers.
- Level-sensitive interrupts: pulse received, counter overflow.
Deliverables
- VHDL core using the CERN coding guidelines.
- VHDL testbench for the core.
- Report with real measurements using spec and fmc-dio-5chttla..
- Documentation for users of the core.
- Demonstration design for the SPEC board.