Project description
The TDC core is a high precision (sub-nanosecond) time to digital conversion core for Xilinx Spartan-6 FPGAs.
Specifications
- Expected precision: 50-100ps (peak to peak).
- Fixed point output:
- Integer part is number of FPGA clocks (coarse counter).
- 13-bit fractional part.
- With a 10ns FPGA clock, LSB corresponds to 1.22ps.
- Typical range: 340ms (using a <25.13>-bit value).
- Number of coarse counter bits configurable with a VHDL generic.
- Latency: 4 to 6 cycles (not including host interface module).
- Multiple channels.
- Configurable with a VHDL generic.
- Calibration logic shared between channels.
- Uses a counter for coarse timing and a calibrated delay line for fine timing.
- Delay line implemented with carry chain (CARRY4) primitives.
- Calibration mechanism:
- at startup (and after receiving a recalibrate command), send random pulses into the delay line (coming from e.g. a on-chip ring oscillator), build histogram, compute delays (as explained in the Fermilab paper), initialize the LUT, and measure the frequency of the compensation ring oscillator.
- for online temperature/voltage compensation, measure again the frequency of the ring oscillator, compare it to the frequency measured at start-up, linearly interpolate the delays, and update the LUT.
- "Wave union" not implemented.
- Output signals (without host interface module):
- Periodic counter overflow.
- Received pulse notification (with counter value + fine timing).
- Optional host/CPU interface module:
- Wishbone slave.
- Configuration and status registers.
- Level-sensitive interrupts: pulse received, counter overflow.
Deliverables
- VHDL core using the CERN coding guidelines.
- VHDL testbench for the core.
- Report with real measurements using spec and fmc-dio-5chttla..
- Documentation for users of the core.
- Demonstration design for the SPEC board.