Change list on the FTRN-AMC schematic 2016-07-26 compared to the schematic from 2016-06-16

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PAGE 3
- updated power tree diagram

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PAGE 4
- replaced DZ2 with same component where symbol is changed, 
   pin numbers are visible, now PIN 1 is KATHODE!!!
   
-  ROOM AUX_MP (top right)
 + added zenner diode DZ5

- DCDC regulators back to reference design, reverted LTM4619 back to LTM4620 
  for FPGA core voltage 1.15V and 2.5V for IO

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PAGE 6
 - fixed comments at RST1, RST2 (corrected text)
 
 - JTAGCON1 will be available on the front panel
   JTAG chain mod: JTAG signals from backplane are connected after  
   buffer DRV1 to CPLD/FPGA JTAG chain with added serial resistors
 
 - JTAG buffer (for USB connector JTAG) output enable is controlled by DIP switch  
 
 - added resistors on JTAG signals towards JTAG switch (R1217, R1218, 1219, 1220)

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PAGE 7
 - WR/FTRN status LEDs replaced with 90deg variant (colors stay the same) 
 
 - added decoupling capacitors for buffers DRVLED1, DRVLED2

 - updated DIS1 connector (change done in common library)
  + pins 3,5,6,18 now have type "Power"  

 - updated USB1 microcontroller symbol (change done in common library)
  + power pins now have type "Power" (previously "Bidirectional" which gave DRC errors)
  
 - updated DRVLED1, DRVLED2 symbol
  + pin 21, Thermal changed type to "passive" (previously "bidirectional")
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PAGE 9
 - WR clock (CLK_125M_WRPLL_N_0) to bank 8D and SYS CLK (CLK_OSC_P_1) to bank 8A
   are reverted to AC-coupling

 - removed MMC_I2C connection between FPGA and MMC, only SPI stays

 - named nets MMC_QUIESCE_OUT_R, MMC_QUIESCE_IN_R between resistors and FPGA
 
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PAGE 10
 - moved HSS_RX_x_1 and HSS_RX_x_2 to bank 3A
 
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PAGE 11
 - updated DRVIOLED1 symbol
  + pin 21, Thermal changed type to "passive", previously "bidirectional"
  
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PAGE 13
- renamed net PRUN_1V15_T to PRUN_1V15
- renamed net PRUN_1V15_C to PRUN_1V15C
- renamed net MMC_VS_V1_15_C to MMC_VS_V1_15C
- renamed net MMC_VS_V1_15_T to MMC_VS_V1_15

- replaced resistor R351 with 2K (previously 1K)

- updated PGOOD nets to match DCDC converter configuration

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PAGE 14
 - JSW1
   + pin  8, net renamed from JTCK_RB to JTCK_SR
   + pin 10, net renamed from JTMS_RB to JTMS_SR 
   + pin 17, net renamed from JTID_RB to JTDI_SR 
   + pin 19, net renamed from JTDO_FB to JTDO_RS 
   
 - added JTAG DIP switch indicator, LED to be placed on front panel
   (Q505, D211, R1227)
  
  AMCPLG1 JTAG is connected first to JDRV1, JDRV2 buffers! 
  JTAG from backplane goes from AMCPLG1 > JDRV2 > JSW1 > CPLD/FGPA or MMC > JSW1 > JDRV1 > AMCPLG1
  
 - power net for JDRV1, JDRV2 connected to V33_MP (previously to V3_3)
   



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Change list on the FTRN-AMC schematic compared to the schematic from 16.12.2015:

PAGE 3
 - updated power tree diagram

PAGE 4
 - LTM4620 DCDC converter replaced with LTM4619
 - FPGA core voltage raised to 1.15V
 - added resistors for adjusting LTM4619 DCDC converter frequency and mode
 - added resistors for optional current sharing configuration of LTM4619 with 1.15V output
 - added 0R resistors and solder jumpers for current mesurements
 - larger values for LED resistors

PAGE 5
 - larger values for LED resistors
 - 1.15V for FPGA VCC

PAGE 7
 - larger values for LED resistors
 
PAGE 9
 - removed AC-coupling resistors on clock lines to FPGA pins
  H15, G15 (from WR PLL)
  C22, C23 (from local OSC crosspoint switch)
  
PAGE 10
 - renamed signals on BANK 4D for controling TCLK buffers (for MTCA.4)
  
PAGE 11,12
 - replaced TVS diode
 - larger values for LED resistors

PAGE 13
 - larger values for LED resistors
 - added MMC analog ground net(AGND)
 - moved JTAG switch to page 14
 - added resistors on MMC JTRST net (JTRTS_MMC)
 - RESET net from JTAG1 (MMC JTAG connector) connected to MMC reset
 - updated PRUN and PGOOD nets to match changes on PAGE 4
 
PAGE 14
 - added buffers for backplane JTAG signals
 - moved JTAG switch from PAGE 13 
 
PAGE 15
 - new TCLK buffers towards backplane 
 
PAGE 17
 - removed AC-coupling capacitors on differential lines between FPGA and buffers for PORTs 12-15
 