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Commits (11)
#############################################################################################
Change list on the FTRN-AMC PCB 2017-03-10 compared to the PCB from 2016-10-11
-------------------------------------------------------------------------------
- added GND layers
- switch S1 for USB microcontroller moved further away from the board edge
so the switch handle does not interfere with crate slot rail
- phase matched differential pairs, PCIe and SFP under 5mil,
other (front panel IO, backpanel IO, clocks) under 0.5mm
- flipped HEX switches
- increased distance between USB connector signals and LEMO center pin
- length matched signals to SPIFLASHX4_1 (FPGA image flash)
- othe minor cleanups (vias, removed/flattened unecesarry line sigments, etc.)
-------------------------------------------------------------------------------
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G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: C:/___PCB_SCH/External/CosyLab/AMC/A/FTRN_AMC_REVA.BRD*
G04 Film Name: Milling*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S051*
G04 Origin Date: Thu Mar 09 16:57:22 2017*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.0000*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.001*%
G75*
%LPD*%
G75*
G54D10*
G01X-880000Y6632500D02*
Y-87500D01*
G01X480000Y-607500D02*
Y-507500D01*
X-280000D01*
Y-87500D01*
X-880000D01*
G01Y6632500D02*
X556000D01*
Y6582500D01*
X1380000D01*
Y6742500D01*
G01X480000Y-607500D02*
X16044500D01*
G01X830000Y6342500D02*
G03Y6182500I0J-80000D01*
G01D02*
X1730000D01*
G01Y6342500D02*
X830000D01*
G01X16044500Y6742500D02*
X1380000D01*
G01X1730000Y6342500D02*
G02Y6182500I0J-80000D01*
G01X16044500Y-607500D02*
X16050000D01*
G01D02*
G03X16100000Y-557500I0J50000D01*
G01D02*
Y-282500D01*
G01X16200000Y-182500D02*
X17180000D01*
G01X16100000Y-282500D02*
G02X16200000Y-182500I100000J0D01*
G01X17180000Y6317500D02*
X16200000D01*
G01D02*
G02X16100000Y6417500I0J100000D01*
G01D02*
Y6692500D01*
G01D02*
G03X16050000Y6742500I-50000J0D01*
G01D02*
X16044500D01*
G01X17180000Y-182500D02*
Y6317500D01*
M02*
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#############################################################################################
Change list on the FTRN-AMC schematic 2016-07-26 compared to the schematic from 2016-07-26
-------------------------------------------------------------------------------
PAGE 8
- named nets for clock signals between AC-coupling caps and CLKSW1 inputs
(D2: CLK100_C_P/N, CLK125_C_P/N)
-------------------------------------------------------------------------------
#############################################################################################
Change list on the FTRN-AMC schematic 2016-07-26 compared to the schematic from 2016-06-16
-------------------------------------------------------------------------------
PAGE 3
- updated power tree diagram
-------------------------------------------------------------------------------
PAGE 4
- replaced DZ2 with same component where symbol is changed,
pin numbers are visible, now PIN 1 is KATHODE!!!
- ROOM AUX_MP (top right)
+ added zenner diode DZ5
- DCDC regulators back to reference design, reverted LTM4619 back to LTM4620
for FPGA core voltage 1.15V and 2.5V for IO
-------------------------------------------------------------------------------
PAGE 6
- fixed comments at RST1, RST2 (corrected text)
- JTAGCON1 will be available on the front panel
JTAG chain mod: JTAG signals from backplane are connected after
buffer DRV1 to CPLD/FPGA JTAG chain with added serial resistors
- JTAG buffer (for USB connector JTAG) output enable is controlled by DIP switch
- added resistors on JTAG signals towards JTAG switch (R1217, R1218, 1219, 1220)
-------------------------------------------------------------------------------
PAGE 7
- WR/FTRN status LEDs replaced with 90deg variant (colors stay the same)
- added decoupling capacitors for buffers DRVLED1, DRVLED2
- updated DIS1 connector (change done in common library)
+ pins 3,5,6,18 now have type "Power"
- updated USB1 microcontroller symbol (change done in common library)
+ power pins now have type "Power" (previously "Bidirectional" which gave DRC errors)
- updated DRVLED1, DRVLED2 symbol
+ pin 21, Thermal changed type to "passive" (previously "bidirectional")
-------------------------------------------------------------------------------
PAGE 9
- WR clock (CLK_125M_WRPLL_N_0) to bank 8D and SYS CLK (CLK_OSC_P_1) to bank 8A
are reverted to AC-coupling
- removed MMC_I2C connection between FPGA and MMC, only SPI stays
- named nets MMC_QUIESCE_OUT_R, MMC_QUIESCE_IN_R between resistors and FPGA
-------------------------------------------------------------------------------
PAGE 10
- moved HSS_RX_x_1 and HSS_RX_x_2 to bank 3A
-------------------------------------------------------------------------------
PAGE 11
- updated DRVIOLED1 symbol
+ pin 21, Thermal changed type to "passive", previously "bidirectional"
-------------------------------------------------------------------------------
PAGE 13
- renamed net PRUN_1V15_T to PRUN_1V15
- renamed net PRUN_1V15_C to PRUN_1V15C
- renamed net MMC_VS_V1_15_C to MMC_VS_V1_15C
- renamed net MMC_VS_V1_15_T to MMC_VS_V1_15
- replaced resistor R351 with 2K (previously 1K)
- updated PGOOD nets to match DCDC converter configuration
-------------------------------------------------------------------------------
PAGE 14
- JSW1
+ pin 8, net renamed from JTCK_RB to JTCK_SR
+ pin 10, net renamed from JTMS_RB to JTMS_SR
+ pin 17, net renamed from JTID_RB to JTDI_SR
+ pin 19, net renamed from JTDO_FB to JTDO_RS
- added JTAG DIP switch indicator, LED to be placed on front panel
(Q505, D211, R1227)
AMCPLG1 JTAG is connected first to JDRV1, JDRV2 buffers!
JTAG from backplane goes from AMCPLG1 > JDRV2 > JSW1 > CPLD/FGPA or MMC > JSW1 > JDRV1 > AMCPLG1
- power net for JDRV1, JDRV2 connected to V33_MP (previously to V3_3)
#######################################################################################
Change list on the FTRN-AMC schematic compared to the schematic from 16.12.2015:
PAGE 3
- updated power tree diagram
PAGE 4
- LTM4620 DCDC converter replaced with LTM4619
- FPGA core voltage raised to 1.15V
- added resistors for adjusting LTM4619 DCDC converter frequency and mode
- added resistors for optional current sharing configuration of LTM4619 with 1.15V output
- added 0R resistors and solder jumpers for current mesurements
- larger values for LED resistors
PAGE 5
- larger values for LED resistors
- 1.15V for FPGA VCC
PAGE 7
- larger values for LED resistors
PAGE 9
- removed AC-coupling resistors on clock lines to FPGA pins
H15, G15 (from WR PLL)
C22, C23 (from local OSC crosspoint switch)
PAGE 10
- renamed signals on BANK 4D for controling TCLK buffers (for MTCA.4)
PAGE 11,12
- replaced TVS diode
- larger values for LED resistors
PAGE 13
- larger values for LED resistors
- added MMC analog ground net(AGND)
- moved JTAG switch to page 14
- added resistors on MMC JTRST net (JTRTS_MMC)
- RESET net from JTAG1 (MMC JTAG connector) connected to MMC reset
- updated PRUN and PGOOD nets to match changes on PAGE 4
PAGE 14
- added buffers for backplane JTAG signals
- moved JTAG switch from PAGE 13
PAGE 15
- new TCLK buffers towards backplane
PAGE 17
- removed AC-coupling capacitors on differential lines between FPGA and buffers for PORTs 12-15
\ No newline at end of file
#############################################################################################
Change list of the FTRN-AMC REVB PCB compared to the REVA PCB from 2016-07-26
Only mechanical changes are described here.
-------------------------------------------------------------------------------
- moved C100 and DIP1 switch towards board center, away from JTAG1 connector
- fixed backplane connector outline (corners), as on Figure 2-12,
DETAIL A, PICMG AMC.0 R2.0 specification document
- fixed backplane connector pins/pads (pin second/third/last mate),
as on Figure 2-13 PICMG AMC.0 R2.0 specification document
- changed board outline: added notches in the backplane connector
"PCB edge implementation specific area"
- added text near DIP1 switch to describe DIP switch functionality
- added OHWR license text and web link to the silk
- added CE, ROHS symbols
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G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: C:/___PCB_SCH/External/CosyLab/AMC/B/FTRN_AMC_REVB.brd*
G04 Film Name: Milling*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S051*
G04 Origin Date: Mon Feb 26 16:38:10 2018*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
G04 Offset: (0.0000 0.0000)*
G04 Mirror: No*
G04 Mode: Positive*
G04 Rotation: 0*
G04 FullContactRelief: No*
G04 UndefLineWidth: 0.0000*
G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX35Y35*MOMM*%
%IR0*IPPOS*OFA0.00000B0.00000*MIA0B0*SFA1.00000B1.00000*%
%ADD10C,.001*%
G75*
%LPD*%
G75*
G54D10*
G01X0Y7240000D02*
Y520000D01*
G01X1360000Y0D02*
Y100000D01*
X600000D01*
Y520000D01*
X0D01*
G01Y7240000D02*
X1436000D01*
Y7190000D01*
X2260000D01*
Y7350000D01*
G01X1360000Y0D02*
X16924500D01*
G01X1710000Y6950000D02*
G03Y6790000I0J-80000D01*
G01D02*
X2610000D01*
G01Y6950000D02*
X1710000D01*
G01X16924500Y7350000D02*
X2260000D01*
G01X2610000Y6950000D02*
G02Y6790000I0J-80000D01*
G01X16924500Y0D02*
X16930000D01*
G01D02*
G03X16980000Y50000I0J50000D01*
G01D02*
Y325000D01*
G01D02*
G02X17080000Y425000I100000J0D01*
G01X17236000D01*
G01X17480900Y540700D02*
X17236000Y425000D01*
G01X17080000Y6925000D02*
G02X16980000Y7025000I0J100000D01*
G01X17236000Y6925000D02*
X17480900Y6809300D01*
G01X17236000Y6925000D02*
X17480900Y6809300D01*
G01X17080000Y6925000D02*
X17236000D01*
G01D02*
X17480900Y6809300D01*
G01X17080000Y6925000D02*
X17236000D01*
G01X16980000Y7025000D02*
Y7300000D01*
G01D02*
G03X16930000Y7350000I-50000J0D01*
G01D02*
X16924500D01*
G01X17585300Y492400D02*
X17603500Y425000D01*
X17980000D01*
G03X18015000Y440000I-770J50130D01*
G01X18060000Y485000D01*
G01X17585300Y492400D02*
G03X17480900Y540700I-72405J-19524D01*
G01Y6809300D02*
G03X17585300Y6857600I31995J67824D01*
G01D02*
X17603500Y6925000D01*
G01X17480900Y6809300D02*
G03X17585300Y6857600I31995J67824D01*
G01D02*
X17603500Y6925000D01*
G01D02*
X17980000D01*
G01X17480900Y6809300D02*
G03X17585300Y6857600I31995J67824D01*
G01D02*
X17603500Y6925000D01*
G01D02*
X17980000D01*
G01D02*
G02X18015000Y6910000I-770J-50130D01*
G01X17980000Y6925000D02*
G02X18015000Y6910000I-770J-50130D01*
G01X18060000Y485000D02*
Y6865000D01*
G01X18015000Y6910000D02*
X18060000Y6865000D01*
G01X18015000Y6910000D02*
X18060000Y6865000D01*
M02*
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