PCI pins pullued up during FPGA boot
During schematic and PCB review of the REVB, Piotr spotted a bug:
"I checked only schematic and I have found one thing that might be
PMC/pcie is not disconnected during FPGA boot.
It may lead to unpredictable state. In worst case CPU will be not able to finish POST (just like in the past).
This is just my guess so if they are 110% sure it might be left as it is."
As a reference for PCI connections between FPGA and PCI/PMC connectors
the schematic  from Altera was used but with a different FPGA
After rechecking the  schematic, Stratix and ArriaV datasheets I found following:
Comparing Stratix and Arria V datasheets there is difference between them during boot, before FPGA enters user mode:
- Stratix has IO output drivers disabled, but internal pull-ups can be enabled OR disabled, in case of , they are disabled
- Arria V GX has IO output drivers disabled, but internal pull-up are
- on the REVB schematic bus switches are enabled, therefore PCI lines would be pulled-up by internal FPGA pull-ups during ArriaV boot, effectively driving PCI bus signals and this might cause issues that Piotr mentioned
Therefore schematic needs to be changed to be on the safe side:
- pull-up added to bus switch enable pins, disabling them on power-up,
before FPGA enters user mode
- FPGA enables bus switches by pulling low bus switch enable pins when it enters user mode (and also disables internal pull-ups)
Schematic is already fixed I am waiting on the PCB to be changed.