fixed dropped jump if followed by multicycle instruction

1cc11f80 · Tomasz Wlostowski · a9fae1ac · 1cc11f80 · 1cc11f80 · 1cc11f80
Commit 1cc11f80 authored May 26, 2015 by Tomasz Wlostowski
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Showing with 134 additions and 112 deletions

main.sv main.sv +36 -1

rv_exec.v rv_exec.v +16 -8

rv_predecode.v rv_predecode.v +4 -0

wave.do wave.do +78 -103

No files found.
--- a/main.sv
+++ b/main.sv
@@ -217,6 +217,36 @@ module main;
   endfunction // decode_regname
   

+   task automatic verify_branch(input [31:0] rs1, input[31:0] rs2, input take, input [2:0] fun);
+      int do_take;
+
+      case(fun)
+	`BRA_EQ: do_take = (rs1 == rs2);
+	`BRA_NEQ: do_take = (rs1 != rs2);
+	`BRA_GE: do_take = $signed(rs1) >= $signed(rs2);
+	`BRA_LT: do_take = $signed(rs1) < $signed(rs2);
+	`BRA_GEU: do_take = rs1 >= rs2;
+	`BRA_LTU: do_take = rs1 < rs2;
+	default:
+	  begin
+	     $error("illegal branch func");
+	     $stop;
+	  end
+	
+      endcase // case (func)
+
+      if(do_take != take)
+	begin
+	   $error("fucked up jump");
+	   $stop;
+
+	end
+      
+      
+   endtask // verify_branch
+   
+   		 
+   
   function automatic string s_hex(int x);
      return $sformatf("%s0x%-08x", x<0?"-":" ", (x<0)?(-x):x);
   endfunction // s_hex
@@ -345,7 +375,11 @@ module main;
 		 opc = "branch";
 		 fun = decode_cond(DUT.d2x_fun);
 //decode_op(DUT.d2x_fun);
-		 args = $sformatf("%-3s %-3s 0x%-08x %s", rs1, rs2, DUT.execute.branch_target, DUT.execute.branch_take?"TAKE":"IGNORE");
+		 args = $sformatf("%-3s %-3s 0x%-08x rs1 %s", rs1, rs2, DUT.execute.branch_target, DUT.execute.branch_take?"TAKE":"IGNORE");
+
+		 verify_branch(DUT.execute.rs1, DUT.execute.rs2, DUT.execute.branch_take,DUT.d2x_fun);
+		 
+		 
 	      end
 	    `OPC_LOAD: 
 	      begin 
@@ -366,6 +400,7 @@ module main;

 	  $display("%08x: %-8s %-3s %s", DUT.execute.d_pc_i, opc, fun, args);
  	  $fwrite(f_exec_log,"%08x: %-8s %-3s %s\n", DUT.execute.d_pc_i, opc, fun, args);
+	  $fwrite(f_exec_log,": PC %08x OP %08x\n", DUT.execute.d_pc_i, DUT.decode.x_ir);
 	  
 	  


--- a/rv_exec.v
+++ b/rv_exec.v
@@ -55,7 +55,7 @@ input		     w_stall_req_i,
   input 	     d_is_shift_i,

   output reg [31:0] f_branch_target_o,
-   output reg 	     f_branch_take_o,
+   output  	     f_branch_take_o,

   output 	     w_load_hazard_o,
   
@@ -104,6 +104,9 @@ input		     w_stall_req_i,
   wire        cmp_equal = (cmp_op1 == cmp_op2);
   wire        cmp_lt = cmp_rs[32];

+   reg 	       f_branch_take;
+   
+   
   // branch condition decoding   
   always@*
     case (d_fun_i)
@@ -203,9 +206,11 @@ input		     w_stall_req_i,
      );


-
   always@(posedge clk_i)
-     shifter_req_d0 <= shifter_req;
+     if(shifter_req_d0 && !x_stall_i)
+       shifter_req_d0 <= 0;
+     else
+       shifter_req_d0 <= shifter_req;
   
   wire shifter_stall_req = shifter_req && !shifter_req_d0;
   
@@ -230,7 +235,8 @@ input		     w_stall_req_i,
   // generate load/store address
   always@*
     begin
-	dm_addr <=  rs1 + $signed(d_imm_i[11:0]);
+	dm_addr <=  rs1 + d_imm_i;
+//[11:0]);

     end

@@ -299,7 +305,7 @@ input		     w_stall_req_i,
   always@(posedge clk_i) 
      if (rst_i) begin
 	 f_branch_target_o <= 0;
-	 f_branch_take_o <= 0;
+	 f_branch_take   <= 0;
 	 w_rd_write_o <= 0;
 	 w_rd_o <= 0;
 	 w_fun_o <= 0;
@@ -310,7 +316,7 @@ input		     w_stall_req_i,
 	 
      end else if (!x_stall_i) begin
 	 f_branch_target_o <= branch_target;
-	 f_branch_take_o <= branch_take && !x_kill_i && d_valid_i;
+	 f_branch_take <= branch_take && !x_kill_i && d_valid_i;

 	 w_rd_o <= d_rd_i;
 	 
@@ -326,16 +332,18 @@ input		     w_stall_req_i,
 	 w_dm_addr_o <= dm_addr;
 	 
      end else begin // if (!x_stall_i)
-	 f_branch_take_o <= 0;
+	 f_branch_take   <= 0;
 	 w_rd_write_o <= 0;
 	 w_load_o <= 0;
 	 w_store_o <= 0;
  
 end // else: !if(rst_i)
+
+   assign f_branch_take_o = f_branch_take;
   

   
-   assign x_stall_req_o = shifter_stall_req || ((is_store || is_load) && !dm_ready_i);
+   assign x_stall_req_o = !f_branch_take && (shifter_stall_req || ((is_store || is_load) && !dm_ready_i));
   assign w_load_hazard_o = d_load_hazard_i;
   


--- a/rv_predecode.v
+++ b/rv_predecode.v
@@ -85,6 +85,8 @@ module rv_decode
 	  rf_rs1_o <= f_rs1;
 	  rf_rs2_o <= f_rs2;
       end
+   reg[31:0] x_ir;
+   
   
   always@(posedge clk_i)
     if(rst_i)
@@ -94,6 +96,8 @@ module rv_decode
       end else if(!d_stall_i) begin
 	  x_valid_o <= f_valid_i && !d_kill_i;
 	  x_pc_o <= f_pc_i;
+	  x_ir <= f_ir_i;
+	  
       end

   wire [4:0] d_opcode = f_ir_i[6:2];

--- a/wave.do
+++ b/wave.do
@@ -36,18 +36,8 @@ add wave -noupdate -group D /main/DUT/decode/x_shamt_o
 add wave -noupdate -group D /main/DUT/decode/x_fun_o
 add wave -noupdate -group D /main/DUT/decode/x_opcode_o
 add wave -noupdate -group D /main/DUT/decode/x_shifter_sign_o
-add wave -noupdate -group D /main/DUT/decode/x_imm_i_o
-add wave -noupdate -group D /main/DUT/decode/x_imm_s_o
-add wave -noupdate -group D /main/DUT/decode/x_imm_b_o
-add wave -noupdate -group D /main/DUT/decode/x_imm_u_o
-add wave -noupdate -group D /main/DUT/decode/x_imm_j_o
-add wave -noupdate -group D /main/DUT/decode/d_ir
 add wave -noupdate -group D /main/DUT/decode/f_rs1
 add wave -noupdate -group D /main/DUT/decode/f_rs2
-add wave -noupdate -group D /main/DUT/decode/d_rs1
-add wave -noupdate -group D /main/DUT/decode/d_rs2
-add wave -noupdate -group D /main/DUT/decode/rd
-add wave -noupdate -group D /main/DUT/decode/opcode
 add wave -noupdate -group RF /main/DUT/regfile/clk_i
 add wave -noupdate -group RF /main/DUT/regfile/rst_i
 add wave -noupdate -group RF /main/DUT/regfile/x_stall_i
@@ -69,91 +59,82 @@ add wave -noupdate -group RF /main/DUT/regfile/write
 add wave -noupdate -group RF /main/DUT/regfile/rs1_bypass
 add wave -noupdate -group RF /main/DUT/regfile/rs2_bypass
 add wave -noupdate -group RF -expand /main/DUT/regfile/bank0/ram
-add wave -noupdate -group X /main/DUT/execute/clk_i
-add wave -noupdate -group X /main/DUT/execute/rst_i
-add wave -noupdate -group X /main/DUT/execute/x_stall_i
-add wave -noupdate -group X /main/DUT/execute/x_kill_i
-add wave -noupdate -group X /main/DUT/execute/x_stall_req_o
-add wave -noupdate -group X /main/DUT/execute/d_pc_i
-add wave -noupdate -group X /main/DUT/execute/d_rd_i
-add wave -noupdate -group X /main/DUT/execute/d_fun_i
-add wave -noupdate -group X /main/DUT/execute/rf_rs1_value_i
-add wave -noupdate -group X /main/DUT/execute/rf_rs2_value_i
-add wave -noupdate -group X /main/DUT/execute/d_valid_i
-add wave -noupdate -group X /main/DUT/execute/d_opcode_i
-add wave -noupdate -group X /main/DUT/execute/d_shifter_sign_i
-add wave -noupdate -group X /main/DUT/execute/d_imm_i_i
-add wave -noupdate -group X /main/DUT/execute/d_imm_s_i
-add wave -noupdate -group X /main/DUT/execute/d_imm_b_i
-add wave -noupdate -group X /main/DUT/execute/d_imm_u_i
-add wave -noupdate -group X /main/DUT/execute/d_imm_j_i
-add wave -noupdate -group X /main/DUT/execute/f_branch_target_o
-add wave -noupdate -group X /main/DUT/execute/f_branch_take_o
-add wave -noupdate -group X /main/DUT/execute/w_fun_o
-add wave -noupdate -group X /main/DUT/execute/w_load_o
-add wave -noupdate -group X /main/DUT/execute/w_store_o
-add wave -noupdate -group X /main/DUT/execute/w_rd_o
-add wave -noupdate -group X /main/DUT/execute/w_rd_value_o
-add wave -noupdate -group X /main/DUT/execute/w_rd_write_o
-add wave -noupdate -group X /main/DUT/execute/w_dm_addr_o
-add wave -noupdate -group X /main/DUT/execute/dm_addr_o
-add wave -noupdate -group X /main/DUT/execute/dm_data_s_o
-add wave -noupdate -group X /main/DUT/execute/dm_data_select_o
-add wave -noupdate -group X /main/DUT/execute/dm_store_o
-add wave -noupdate -group X /main/DUT/execute/dm_load_o
-add wave -noupdate -group X /main/DUT/execute/dm_ready_i
-add wave -noupdate -group X /main/DUT/execute/rs1
-add wave -noupdate -group X /main/DUT/execute/rs2
-add wave -noupdate -group X /main/DUT/execute/alu_op1
-add wave -noupdate -group X /main/DUT/execute/alu_op2
-add wave -noupdate -group X /main/DUT/execute/alu_result
-add wave -noupdate -group X /main/DUT/execute/rd_value
-add wave -noupdate -group X /main/DUT/execute/branch_take
-add wave -noupdate -group X /main/DUT/execute/branch_condition_met
-add wave -noupdate -group X /main/DUT/execute/branch_target
-add wave -noupdate -group X /main/DUT/execute/dm_addr
-add wave -noupdate -group X /main/DUT/execute/dm_data_s
-add wave -noupdate -group X /main/DUT/execute/dm_select_s
-add wave -noupdate -group X /main/DUT/execute/rd_write
-add wave -noupdate -group X /main/DUT/execute/cmp_sign_ext
-add wave -noupdate -group X /main/DUT/execute/cmp_op1
-add wave -noupdate -group X /main/DUT/execute/cmp_op2
-add wave -noupdate -group X /main/DUT/execute/cmp_rs
-add wave -noupdate -group X /main/DUT/execute/cmp_equal
-add wave -noupdate -group X /main/DUT/execute/cmp_lt
-add wave -noupdate -group X /main/DUT/execute/is_add
-add wave -noupdate -group X /main/DUT/execute/shifter_result
-add wave -noupdate -group X /main/DUT/execute/alu_op_signext
-add wave -noupdate -group X /main/DUT/execute/alu_addsub_op1
-add wave -noupdate -group X /main/DUT/execute/alu_addsub_op2
-add wave -noupdate -group X /main/DUT/execute/alu_addsub_result
-add wave -noupdate -group X /main/DUT/execute/shifter_req_d0
-add wave -noupdate -group X /main/DUT/execute/shifter_req
-add wave -noupdate -group X /main/DUT/execute/shifter_stall_req
-add wave -noupdate -group X /main/DUT/execute/is_load
-add wave -noupdate -group X /main/DUT/execute/is_store
-add wave -noupdate -expand -group W /main/DUT/writeback/clk_i
-add wave -noupdate -expand -group W /main/DUT/writeback/rst_i
-add wave -noupdate -expand -group W /main/DUT/writeback/w_stall_i
-add wave -noupdate -expand -group W /main/DUT/writeback/w_stall_req_o
-add wave -noupdate -expand -group W /main/DUT/writeback/interlock_d
-add wave -noupdate -expand -group W /main/DUT/writeback/interlock
-add wave -noupdate -expand -group W /main/DUT/writeback/interlock_stall_req
-add wave -noupdate -expand -group W /main/DUT/writeback/x_fun_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_load_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_load_hazard_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_store_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_dm_addr_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_rd_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_rd_value_i
-add wave -noupdate -expand -group W /main/DUT/writeback/x_rd_write_i
-add wave -noupdate -expand -group W /main/DUT/writeback/dm_data_l_i
-add wave -noupdate -expand -group W /main/DUT/writeback/dm_load_done_i
-add wave -noupdate -expand -group W /main/DUT/writeback/dm_store_done_i
-add wave -noupdate -expand -group W /main/DUT/writeback/rf_rd_value_o
-add wave -noupdate -expand -group W /main/DUT/writeback/rf_rd_o
-add wave -noupdate -expand -group W /main/DUT/writeback/rf_rd_write_o
-add wave -noupdate -expand -group W /main/DUT/writeback/load_value
+add wave -noupdate -expand -group X /main/DUT/execute/clk_i
+add wave -noupdate -expand -group X /main/DUT/execute/rst_i
+add wave -noupdate -expand -group X /main/DUT/execute/x_stall_i
+add wave -noupdate -expand -group X /main/DUT/execute/x_kill_i
+add wave -noupdate -expand -group X /main/DUT/execute/x_stall_req_o
+add wave -noupdate -expand -group X /main/DUT/execute/d_pc_i
+add wave -noupdate -expand -group X /main/DUT/execute/d_rd_i
+add wave -noupdate -expand -group X /main/DUT/execute/d_fun_i
+add wave -noupdate -expand -group X /main/DUT/execute/rf_rs1_value_i
+add wave -noupdate -expand -group X /main/DUT/execute/rf_rs2_value_i
+add wave -noupdate -expand -group X /main/DUT/execute/d_valid_i
+add wave -noupdate -expand -group X /main/DUT/execute/d_opcode_i
+add wave -noupdate -expand -group X /main/DUT/execute/d_shifter_sign_i
+add wave -noupdate -expand -group X /main/DUT/execute/f_branch_target_o
+add wave -noupdate -expand -group X /main/DUT/execute/f_branch_take_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_fun_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_load_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_store_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_rd_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_rd_value_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_rd_write_o
+add wave -noupdate -expand -group X /main/DUT/execute/w_dm_addr_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_addr_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_data_s_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_data_select_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_store_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_load_o
+add wave -noupdate -expand -group X /main/DUT/execute/dm_ready_i
+add wave -noupdate -expand -group X /main/DUT/execute/rs1
+add wave -noupdate -expand -group X /main/DUT/execute/rs2
+add wave -noupdate -expand -group X /main/DUT/execute/alu_op1
+add wave -noupdate -expand -group X /main/DUT/execute/alu_op2
+add wave -noupdate -expand -group X /main/DUT/execute/alu_result
+add wave -noupdate -expand -group X /main/DUT/execute/rd_value
+add wave -noupdate -expand -group X /main/DUT/execute/branch_take
+add wave -noupdate -expand -group X /main/DUT/execute/branch_condition_met
+add wave -noupdate -expand -group X /main/DUT/execute/branch_target
+add wave -noupdate -expand -group X /main/DUT/execute/dm_addr
+add wave -noupdate -expand -group X /main/DUT/execute/dm_data_s
+add wave -noupdate -expand -group X /main/DUT/execute/dm_select_s
+add wave -noupdate -expand -group X /main/DUT/execute/rd_write
+add wave -noupdate -expand -group X /main/DUT/execute/cmp_op1
+add wave -noupdate -expand -group X /main/DUT/execute/cmp_op2
+add wave -noupdate -expand -group X /main/DUT/execute/cmp_rs
+add wave -noupdate -expand -group X /main/DUT/execute/cmp_equal
+add wave -noupdate -expand -group X /main/DUT/execute/cmp_lt
+add wave -noupdate -expand -group X /main/DUT/execute/shifter_result
+add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_op1
+add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_op2
+add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_result
+add wave -noupdate -expand -group X /main/DUT/execute/shifter_req_d0
+add wave -noupdate -expand -group X /main/DUT/execute/shifter_req
+add wave -noupdate -expand -group X /main/DUT/execute/shifter_stall_req
+add wave -noupdate -expand -group X /main/DUT/execute/is_load
+add wave -noupdate -expand -group X /main/DUT/execute/is_store
+add wave -noupdate -group W /main/DUT/writeback/clk_i
+add wave -noupdate -group W /main/DUT/writeback/rst_i
+add wave -noupdate -group W /main/DUT/writeback/w_stall_i
+add wave -noupdate -group W /main/DUT/writeback/w_stall_req_o
+add wave -noupdate -group W /main/DUT/writeback/interlock_d
+add wave -noupdate -group W /main/DUT/writeback/interlock
+add wave -noupdate -group W /main/DUT/writeback/x_fun_i
+add wave -noupdate -group W /main/DUT/writeback/x_load_i
+add wave -noupdate -group W /main/DUT/writeback/x_load_hazard_i
+add wave -noupdate -group W /main/DUT/writeback/x_store_i
+add wave -noupdate -group W /main/DUT/writeback/x_dm_addr_i
+add wave -noupdate -group W /main/DUT/writeback/x_rd_i
+add wave -noupdate -group W /main/DUT/writeback/x_rd_value_i
+add wave -noupdate -group W /main/DUT/writeback/x_rd_write_i
+add wave -noupdate -group W /main/DUT/writeback/dm_data_l_i
+add wave -noupdate -group W /main/DUT/writeback/dm_load_done_i
+add wave -noupdate -group W /main/DUT/writeback/dm_store_done_i
+add wave -noupdate -group W /main/DUT/writeback/rf_rd_value_o
+add wave -noupdate -group W /main/DUT/writeback/rf_rd_o
+add wave -noupdate -group W /main/DUT/writeback/rf_rd_write_o
+add wave -noupdate -group W /main/DUT/writeback/load_value
 add wave -noupdate -group Top /main/DUT/clk_i
 add wave -noupdate -group Top /main/DUT/rst_i
 add wave -noupdate -group Top /main/DUT/im_addr_o
@@ -192,12 +173,6 @@ add wave -noupdate -group Top /main/DUT/d2x_shamt
 add wave -noupdate -group Top /main/DUT/d2x_fun
 add wave -noupdate -group Top /main/DUT/d2x_opcode
 add wave -noupdate -group Top /main/DUT/d2x_shifter_sign
-add wave -noupdate -group Top /main/DUT/d2x_imm_i
-add wave -noupdate -group Top /main/DUT/d2x_imm_s
-add wave -noupdate -group Top /main/DUT/d2x_imm_u
-add wave -noupdate -group Top /main/DUT/d2x_imm_b
-add wave -noupdate -group Top /main/DUT/d2x_imm_j
-add wave -noupdate -group Top /main/DUT/d_load_hazard
 add wave -noupdate -group Top /main/DUT/d_stall
 add wave -noupdate -group Top /main/DUT/d_kill
 add wave -noupdate -group Top /main/DUT/x2w_rd
@@ -220,7 +195,7 @@ add wave -noupdate -group Top /main/DUT/w_stall_req
 add wave -noupdate -group Top /main/DUT/x2f_bra_d0
 add wave -noupdate -group Top /main/DUT/x2f_bra_d1
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {157107 ps} 0}
+WaveRestoreCursors {{Cursor 1} {31985000 ps} 0}
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -235,4 +210,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ps
 update
-WaveRestoreZoom {1562594 ps} {1707232 ps}
+WaveRestoreZoom {13501336 ps} {50528664 ps}