The uRV core
Project description
The uRV (Micro RISC-V) is a small footprint 32-bit RISC-V processor core intended for embedded real-time applications. uRV is targeted primarily for use as a soft CPU core in FPGAs.
Features
- Supports RV32IM instruction set. Division and multiply high instructions are optional and can be emulated to lower the FPGA footprint.
- Target: FPGAs.
- 4-stage pipeline (FDXW).
- All instructions except taken branches/division in one clock cycle.
- Code execution from internal memory block.
- Wishbone bus (version B.4) for peripheral access.
- Simple interrupt handling.
- Verilog RTL code.
Contacts
- Tomasz Włostowski (CERN)
Status
Date | Event |
19-05-2015 | First version. |
06-08-2015 | CoreMark |
13-05-2015 | Created the urv-core project on OHWR.org. |
8 October 2015