VHDL Style Guide
Project description
This project defines the coding style for VHDL files and provides a tool to check the rules.
A text document contains a list of rules, like:
==== [PortsName] [M] Ports name
Ports name must be in lower case (as ruled by Identifiers), but must also have
a suffix:
* '_i' for normal input.
* '_o' for normal output.
* '_b' for bidirectional port.
The suffix must be the last one.
Reason: Helps to specify the purpose of a port, makes the dataflow more
obvious.
A tool has been developed to automatically enforce the rules. For this file:
library ieee;
use ieee.std_logic_1164.all;
entity example is
port (clk_i : in std_logic;
incorrect : out std_logic);
end example;
The tool will generate this message for the above rule:
./ex1.vhdl:6:9: [PortsName] out port 'incorrect' must end with '_o'
Project information
- VHDL Style Guide (pdf generated from the master) or text description (the master)
-
Python tool
vhdllint-ohwr
can be used to detect style violations
- see the README file for build and use instructions
- Executable for Windows, an easy to install command-line tool
Contacts
- Tristan Gingold - CERN
Status
Date | Event |
---|---|
13-10-2017 | Work started on VHDL Coding Style document. |
08-12-2017 | Review of VHDL Coding Style document. |
23-03-2018 | Tool published. |
26 March 2018