Commit f7ea7ecc authored by Greg's avatar Greg

HDL for FPGA and CPLD added

parent 6b26135a
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# VME_BRIDGE_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM570F256C3
set_global_assignment -name TOP_LEVEL_ENTITY VME_BRIDGE
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:16:17 MAY 02, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
set_location_assignment PIN_J16 -to adrsel[0]
set_location_assignment PIN_H16 -to adrsel[1]
set_location_assignment PIN_G16 -to adrsel[2]
set_location_assignment PIN_F15 -to adrsel[3]
set_location_assignment PIN_L15 -to adrsel[4]
set_location_assignment PIN_L16 -to adrsel[5]
set_location_assignment PIN_K15 -to adrsel[6]
set_location_assignment PIN_K16 -to adrsel[7]
set_location_assignment PIN_J12 -to clk
set_location_assignment PIN_D15 -to FPGA_RESET
set_location_assignment PIN_R16 -to xdata[8]
set_location_assignment PIN_T13 -to xdata[9]
set_location_assignment PIN_T12 -to xdata[10]
set_location_assignment PIN_N12 -to xdata[4]
set_location_assignment PIN_R11 -to xdata[2]
set_location_assignment PIN_P12 -to xdata[13]
set_location_assignment PIN_T11 -to xdata[11]
set_location_assignment PIN_R12 -to xdata[1]
set_location_assignment PIN_R10 -to xdata[3]
set_location_assignment PIN_P11 -to xdata[5]
set_location_assignment PIN_M8 -to xdata[0]
set_location_assignment PIN_T10 -to xdata[12]
set_location_assignment PIN_P10 -to xdata[14]
set_location_assignment PIN_R9 -to xdsn[1]
set_location_assignment PIN_T9 -to xlwordn
set_location_assignment PIN_T8 -to xwriten
set_location_assignment PIN_P9 -to xdata[6]
set_location_assignment PIN_R8 -to xdsn[0]
set_location_assignment PIN_P8 -to xdata[15]
set_location_assignment PIN_T7 -to xaddr[23]
set_location_assignment PIN_P7 -to xdata[7]
set_location_assignment PIN_R7 -to xam[5]
set_location_assignment PIN_P6 -to xam[1]
set_location_assignment PIN_T6 -to xaddr[22]
set_location_assignment PIN_R5 -to xam[2]
set_location_assignment PIN_R6 -to xam[0]
set_location_assignment PIN_T5 -to xaddr[21]
set_location_assignment PIN_N5 -to xaddr[11]
set_location_assignment PIN_T4 -to xaddr[20]
set_location_assignment PIN_R4 -to xas
set_location_assignment PIN_P4 -to xaddr[10]
set_location_assignment PIN_R1 -to xaddr[19]
set_location_assignment PIN_R3 -to xaddr[4]
set_location_assignment PIN_P2 -to xam[3]
set_location_assignment PIN_N3 -to xaddr[3]
set_location_assignment PIN_N1 -to xaddr[18]
set_location_assignment PIN_N2 -to xiackn
set_location_assignment PIN_M1 -to xiackinn
set_location_assignment PIN_M4 -to xaddr[9]
set_location_assignment PIN_L2 -to xaddr[15]
set_location_assignment PIN_M3 -to xaddr[2]
set_location_assignment PIN_L1 -to xaddr[16]
set_location_assignment PIN_M2 -to xaddr[17]
set_location_assignment PIN_K2 -to xaddr[14]
set_location_assignment PIN_L4 -to xaddr[8]
set_location_assignment PIN_K1 -to xam[4]
set_location_assignment PIN_L3 -to xaddr[1]
set_location_assignment PIN_J2 -to xaddr[13]
set_location_assignment PIN_K3 -to xiackoutn
set_location_assignment PIN_J1 -to xaddr[7]
set_location_assignment PIN_J3 -to xdata[24]
set_location_assignment PIN_H1 -to xaddr[6]
set_location_assignment PIN_H3 -to xdata[25]
set_location_assignment PIN_H2 -to xaddr[12]
set_location_assignment PIN_G3 -to xdata[26]
set_location_assignment PIN_G1 -to xaddr[5]
set_location_assignment PIN_F3 -to xdata[27]
set_location_assignment PIN_E2 -to xdata[20]
set_location_assignment PIN_F1 -to xdata[23]
set_location_assignment PIN_E3 -to xdata[28]
set_location_assignment PIN_F2 -to xdata[22]
set_location_assignment PIN_E4 -to xdata[29]
set_location_assignment PIN_E1 -to xdata[21]
set_location_assignment PIN_D2 -to xdata[18]
set_location_assignment PIN_D1 -to xdata[19]
set_location_assignment PIN_D3 -to xdata[30]
set_location_assignment PIN_C2 -to xdata[31]
set_location_assignment PIN_B1 -to xdata[17]
set_location_assignment PIN_A2 -to xdata[16]
set_location_assignment PIN_C4 -to xdtack
set_location_assignment PIN_P15 -to xbufdir
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_A5 -to C_EXT[4]
set_location_assignment PIN_B6 -to C_EXT[6]
set_location_assignment PIN_D5 -to C_EXT[3]
set_location_assignment PIN_A6 -to C_EXT[5]
set_location_assignment PIN_B3 -to RVD0
set_location_assignment PIN_D4 -to RVD1
set_location_assignment PIN_A4 -to CPU_INT
set_location_assignment PIN_H12 -to CPLD_CLK
set_location_assignment PIN_B5 -to xbufoen[0]
set_location_assignment PIN_G2 -to xbufoen[1]
set_location_assignment PIN_A7 -to C_EXT[7]
set_location_assignment PIN_A8 -to C_EXT[8]
set_location_assignment PIN_C7 -to C_EXT[2]
set_location_assignment PIN_B4 -to C_EXT[1]
set_location_assignment PIN_C6 -to Main_CK_enable
set_location_assignment PIN_H5 -to PCI_CLK
set_location_assignment PIN_D11 -to RSV3
set_location_assignment PIN_J5 -to RVD12
set_location_assignment PIN_C3 -to RVD13
set_location_assignment PIN_N15 -to spi_CS
set_location_assignment PIN_M15 -to SPI_SCK
set_location_assignment PIN_N16 -to SPI_SO
set_location_assignment PIN_M16 -to SPI_SI
set_location_assignment PIN_T2 -to RVD11
set_location_assignment PIN_A9 -to reconfig
set_location_assignment PIN_C5 -to xirq
set_location_assignment PIN_A10 -to CPLD_STAT
set_location_assignment PIN_P5 -to xsysreset
set_global_assignment -name VHDL_FILE shiftreg.vhd
set_global_assignment -name VHDL_FILE spi_link.vhd
set_global_assignment -name VHDL_FILE clock_divider.vhd
set_global_assignment -name VHDL_FILE types.vhd
set_global_assignment -name VHDL_FILE as_programmer.vhd
set_global_assignment -name VHDL_FILE vme_bridge.vhd
set_global_assignment -name VHDL_FILE VME_CONTROLLER.vhd
set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
set_global_assignment -name FMAX_REQUIREMENT "55 MHz" -section_id "CLK 50"
set_instance_assignment -name CLOCK_SETTINGS "CLK 50" -to clk
set_location_assignment PIN_T15 -to FPGA_AD[0]
set_location_assignment PIN_R14 -to FPGA_AD[1]
set_location_assignment PIN_R13 -to FPGA_AD[2]
set_location_assignment PIN_P14 -to FPGA_AD[3]
set_location_assignment PIN_P13 -to FPGA_AD[4]
set_location_assignment PIN_N14 -to FPGA_AD[5]
set_location_assignment PIN_N13 -to FPGA_AD[6]
set_location_assignment PIN_C9 -to FPGA_AD[7]
set_location_assignment PIN_M13 -to FPGA_AD[8]
set_location_assignment PIN_L14 -to FPGA_AD[9]
set_location_assignment PIN_L13 -to FPGA_AD[10]
set_location_assignment PIN_K14 -to FPGA_AD[11]
set_location_assignment PIN_E15 -to FPGA_AD[12]
set_location_assignment PIN_J15 -to FPGA_AD[13]
set_location_assignment PIN_J14 -to FPGA_AD[14]
set_location_assignment PIN_H15 -to FPGA_AD[15]
set_location_assignment PIN_D16 -to FPGA_TRDYn
set_location_assignment PIN_C15 -to FPGA_IRDYn
set_location_assignment PIN_E16 -to FPGA_INTn
set_location_assignment PIN_F16 -to FPGA_FRAMEn
set_location_assignment PIN_C10 -to FPGA_BEn[0]
set_location_assignment PIN_C8 -to FPGA_BEn[1]
set_location_assignment PIN_M9 -to resetn
set_global_assignment -name VECTOR_WAVEFORM_FILE VME_BRIDGE.vwf
set_location_assignment PIN_H14 -to test_lines[16]
set_location_assignment PIN_G15 -to test_lines[17]
set_location_assignment PIN_G14 -to test_lines[18]
set_location_assignment PIN_F14 -to test_lines[19]
set_location_assignment PIN_F13 -to test_lines[20]
set_location_assignment PIN_E14 -to test_lines[21]
set_location_assignment PIN_E13 -to test_lines[22]
set_location_assignment PIN_D14 -to test_lines[23]
set_location_assignment PIN_C14 -to test_lines[24]
set_location_assignment PIN_D13 -to test_lines[25]
set_location_assignment PIN_C13 -to test_lines[26]
set_location_assignment PIN_B14 -to test_lines[27]
set_location_assignment PIN_C12 -to test_lines[28]
set_location_assignment PIN_B13 -to test_lines[29]
set_location_assignment PIN_D12 -to test_lines[30]
set_location_assignment PIN_C11 -to test_lines[31]
set_location_assignment PIN_B16 -to RSV1
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_A15 -to CPLD_prog_nCONFIG
set_location_assignment PIN_A13 -to CPLD_prog_DCLK
set_location_assignment PIN_B12 -to CPLD_prog_CONF_DONE
set_location_assignment PIN_A12 -to CPLD_prog_DATA
set_location_assignment PIN_B11 -to CPLD_PROG_nCE
set_location_assignment PIN_A11 -to CPLD_prog_nCS
set_location_assignment PIN_B10 -to CPLD_prog_ASDI
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clkdivider is
generic (
divider : integer := 2); -- number of clocks to generate enable pulse
port (
clk : in std_logic; -- general clock
reset : in std_logic; -- async reset
clkenable : out std_logic); -- clock enable used to turn on the clock
end clkdivider;
architecture v1 of clkdivider is
begin -- v1
-- purpose: counts down to zero and when at zero, then it generates clkenable pulse which is exactly 1 tick lock
-- type : sequential
-- inputs : clk, reset
count: process (clk, reset)
variable counter : integer range divider downto 0;
-- counter stuff
begin -- process count
if reset = '0' then -- asynchronous reset (active low)
counter := divider; -- set the state to the divider val.
elsif clk'event and clk = '0' then -- rising clock edge
counter := counter - 1; -- decrease counts
if counter = 0 then
counter := divider;
clkenable <= '1';
else
clkenable <= '0';
end if;
end if;
end process count;
end v1;
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: shiftreg.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY shiftreg IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
END shiftreg;
ARCHITECTURE SYN OF shiftreg IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC ;
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
shiftout <= sub_wire1;
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 8
)
PORT MAP (
enable => enable,
load => load,
sclr => sclr,
clock => clock,
data => data,
shiftin => shiftin,
q => sub_wire0,
shiftout => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_inst.vhd FALSE
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity spi_link is
PORT
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
SCK : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
SCS : in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
command_out : out STD_LOGIC_VECTOR( 7 downto 0);
write_en : out STD_LOGIC;
transfer_done : out STD_LOGIC;
byte_sel : out STD_LOGIC_VECTOR (3 downto 0);
addr_sel : out STD_LOGIC_VECTOR (1 downto 0);
testout : out STD_LOGIC_VECTOR (7 downto 0)
);
end spi_link ;
architecture a of spi_link is
TYPE STATE_TYPE IS (
idle,
cs_low,
clk_h,
wait_clk_l,
clk_l,
latch_cmd,
latch_byte,
transfer_end
);
SIGNAL state: STATE_TYPE;
signal bit_count : integer range 0 to 8;
signal byte_count : integer range 0 to 7;
signal command : std_logic_vector(7 downto 0);
signal write_nread : std_logic;
signal shift_dat_in : std_logic_vector(7 downto 0);
signal shift_dat_out : std_logic_vector(7 downto 0);
signal shift_en : std_logic;
signal shift_load : std_logic;
signal shift_sclr,SCK_synch,SDI_synch,SCS_synch,
update_byte,
load_byte,
transfer_done_tmp,transfer_done_edge_det,
shift_din : std_logic;
signal byte_sel_tmp : std_logic_vector(3 downto 0);
component shiftreg
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
end component;
begin -- a
--***********************************************************************************************************************************************
--******************************************* main control state machine *********************************************************************
--***********************************************************************************************************************************************
--input signals synchronisation
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
SCK_synch <= '0';
SDI_synch <= '0';
SCS_synch <= '0';
ELSIF clk'EVENT AND clk = '0' THEN
SCK_synch <= SCK;
SDI_synch <= SDI;
SCS_synch <= SCS;
end if;
end process;
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
state <= idle;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle =>
byte_count <= 0;
command <= (others => '0');
IF SCS_synch = '0' THEN
state <=cs_low;
END IF;
when cs_low =>
bit_count <= 8;
IF SCK_synch = '1' THEN
state <=clk_h;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when clk_h =>
bit_count <= bit_count - 1;
state <=wait_clk_l;
when wait_clk_l =>
IF SCK_synch = '0' THEN
state <=clk_l;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when clk_l =>
IF bit_count = 0 and byte_count = 0 THEN
state <=latch_cmd;
ELSIF bit_count = 0 and byte_count /= 0 THEN
state <=latch_byte;
ELSIF SCK_synch = '1' THEN
state <=clk_h;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when latch_cmd =>
byte_count <= byte_count + 1 ;
command <= shift_dat_out;
state <=cs_low;
when latch_byte =>
byte_count <= byte_count + 1 ;
IF byte_count = 6 THEN
state <=transfer_end;
ELSIF SCS_synch = '1' THEN
state <=idle;
else
state <=cs_low;
END IF;
when transfer_end =>
IF SCS_synch = '1' THEN
state <=idle;
END IF;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
shift_sclr <= '1' when idle,
'0' when cs_low,
'0' when clk_h,
'0' when clk_l,
'0' when others;
WITH state SELECT
shift_en <= '0' when idle,
'1' when clk_h,
'1' when cs_low,
'0' when others;
WITH state SELECT
update_byte <= '0' when idle,
'1' when latch_byte,
'0' when others;
WITH state SELECT
load_byte <= '0' when idle,
'1' when cs_low,
'0' when others;
WITH state SELECT
transfer_done_tmp <= '0' when idle,
'1' when transfer_end,
'0' when others;
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
transfer_done_edge_det <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
transfer_done_edge_det <= transfer_done_tmp;
transfer_done <= transfer_done_tmp and not transfer_done_edge_det;
end if;
end process;
WITH byte_count SELECT
byte_sel_tmp <= "1000" when 3,
"0100" when 4,
"0010" when 5,
"0001" when 6,
"0000" when others;
byte_sel <= byte_sel_tmp;
addr_sel(1) <= '1' when state = latch_byte and byte_count = 1 else '0';
addr_sel(0) <= '1' when state = latch_byte and byte_count = 2 else '0';
write_nread <= command(7);
--read / write selection
shift_load <= '1' when load_byte = '1' and write_nread = '0' else '0';
write_en <= '1' when update_byte = '1' and write_nread = '1' else '0' ;
--shift_din <= SDI_synch when write_nread = '1' else '0' ;
shift_din <= SDI_synch when (write_nread = '1' or byte_count < 3) else '0' ;
command_out <= command;
shiftreg_1: shiftreg
port map (
clock => clk,
data => shift_dat_in,
enable => shift_en,
load => shift_load,
sclr => shift_sclr,
shiftin => shift_din,
q => shift_dat_out,
shiftout => SDO);
shift_dat_in <= data_in;
data_out <= shift_dat_out;
testout(0) <= shift_din;
testout(1) <= shift_en;
testout(2) <= shift_load;
testout(3) <= shift_sclr;
testout(7 downto 4) <= shift_dat_out (7 downto 4);
end a ;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package types is
-- std_logic_vector types - start with V
subtype VWord is std_logic_vector(15 downto 0); -- 16 bit word
subtype VQWord is std_logic_vector(23 downto 0); -- 24 bit vector
subtype SQWord is signed(23 downto 0); -- 24bit signed to use in arithmetics
subtype SWord is signed(15 downto 0); -- 16 bit signed stuff
subtype SByte is signed(7 downto 0); -- 8 bit signed
subtype VByte is std_logic_vector(7 downto 0); -- 8 bit unsigned vector
subtype VLong is std_logic_vector(31 downto 0); -- 32bit register
-- integer types start with I
subtype IUINT8 is integer range 0 to 255; -- integer range
subtype IUINT4 is integer range 0 to 15; -- 4 bit integer
subtype IADCAddr is integer range 6 downto 0; -- ADC address to read
subtype IQWord is integer range 0 to 16777215; -- 24 bits integer
subtype ISQWord is integer range -8388608 to 8388607; -- signed 24 bits number
-- array of vectors start with AV
type AVADCMEM is array (5 downto 0) of SWord; -- ADC memory registers
type AVACCUMULATOR is array (5 downto 0) of SQWord; -- averager
type AIACCUMULATOR is array (5 downto 0) of ISQWord; -- integer averager
type AVADCOFS is array (5 downto 0) of SWord; -- ADC offsets
type SHAREDREGISTERS is array (NATURAL range <>) of VLong;
end types;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.Types.all;
entity vme_bridge is
port (
-- general part:
resetn : in std_logic; -- reset input, asynchronous
clk : in std_logic; -- 50MHz clk input
-- vme64x part:
xdata : inout std_logic_vector(31 downto 0); -- vme data bus
xaddr : in std_logic_vector(23 downto 1); -- vme address bus
xam : in std_logic_vector(5 downto 0); -- vme address modifier
xbufdir : out std_logic; -- vme buffer direction register
xiackoutn : out std_logic; -- interrupt acknowledge output
xiackinn : in std_logic; -- interrupt ack input
xiackn : in std_logic; -- interrupt acknowledge
xas : in std_logic; -- vme address strobe
xlwordn : in std_logic; -- lword of vme
xdsn : in std_logic_vector(1 downto 0); -- data strobes
xwriten : in std_logic; -- write from vme
xdtack : out std_logic; -- vme data acknowledge
xbufoen : out std_logic_vector(1 downto 0); -- vme buffers output enable
xirq : out std_logic; -- interrupt requesters
xsysreset : in std_logic; -- sysfail request out
-- cpld only stuff:
adrsel : in std_logic_vector(7 downto 0); -- address selector headers
-- put on cpld header conn.
-- test output:
C_EXT : out std_logic_vector(9 downto 1); -- for testing. to be erased later on
--reserved lines
CPLD_CLK : in std_logic; -- 212MHz clock
RSV3 : out std_logic;
RSV1 : out std_logic; --devsel
CPU_INT : out std_logic;
RVD1 : in std_logic;
RVD0 : in std_logic;
RVD11 : in std_logic;
RVD13 : in std_logic;
RVD12 : in std_logic;
test_lines : out std_logic_vector(31 downto 16);
PCI_CLK : out std_logic;
Main_CK_enable : out std_logic;
-- spi interface for accessing the EEPROM configuration memory + serial
-- number chip
spi_CS : IN std_logic; -- SPI slave select
SPI_SI : in std_logic; -- master in. We are master
SPI_SO : out std_logic; -- master out
SPI_SCK : in std_logic; -- we provide clock
-- fpga configuration stuff:
CPLD_prog_nCONFIG : out std_logic; -- active serial nconfig
CPLD_PROG_nCE : out std_logic; -- activeserial chip enable for fpga
CPLD_prog_CONF_DONE : in std_logic; -- activeserial CONF_DONE
CPLD_prog_DCLK : out std_logic; -- activeserial clock
CPLD_prog_DATA : in std_logic; -- activeserial output
CPLD_prog_ASDI : out std_logic; -- activeserial dataout
CPLD_prog_nCS : out std_logic; -- activeserial ncso
reconfig : in std_logic;
CPLD_STAT : out std_logic; -- LED on the front panel
FPGA_RESET : out std_logic; -- reset fpga signal
-- PCI-like multiplexed communication
-- address/data bus is 16 bit wide, BE0,BE1 are used as data strobes and command lines like in PCI
FPGA_IRDYn : out std_logic; -- CPLD not ready
FPGA_TRDYn : in std_logic; -- FPGA not ready
FPGA_FRAMEn : out std_logic; -- start of transfer
FPGA_AD : inout std_logic_vector(15 downto 0); -- muletiplexed PCI-like address and data
FPGA_BEn : out std_logic_vector(1 downto 0); -- word strobes / command: 01- read, 11 - write
FPGA_INTn : in std_logic --interrupt
);
end vme_bridge;
architecture V1 of vme_bridge is
-------------------------------------------------------------------------------
-- component definitions:
-------------------------------------------------------------------------------
-- generic vme interface
component VME_CONTROLLER
port (
reset : in std_logic;
CLK : in std_logic;
v_am : IN STD_LOGIC_VECTOR(5 downto 0);
n_v_ds : IN STD_LOGIC_VECTOR(1 downto 0);
n_v_as : IN STD_LOGIC;
n_v_lw : IN STD_LOGIC;
n_v_iackin : IN STD_LOGIC;
n_v_write : IN STD_LOGIC;
n_v_sys_res : IN STD_LOGIC;
v_dtack : OUT STD_LOGIC;
v_berr : OUT STD_LOGIC;
n_v_irq : OUT STD_LOGIC;
n_v_iackout : OUT STD_LOGIC;
v_ddir : OUT STD_LOGIC;
n_v_doe : OUT STD_LOGIC_VECTOR(1 downto 0);
va : IN STD_LOGIC_VECTOR(23 downto 1);
vd : INOUT STD_LOGIC_VECTOR(31 downto 0);
ModuleAddr : in std_logic_vector(7 downto 0);
spi_CS : in std_logic;
SPI_SI : in std_logic;
SPI_SO : out std_logic;
SPI_CLK : in std_logic;
SPI_INT : out std_logic;
EXT_out : OUT STD_LOGIC_VECTOR(9 downto 1);
test_out : OUT STD_LOGIC_VECTOR(31 downto 16);
fpga_nconfig : out std_logic;
fpga_nce : out std_logic;
as_asdo : out std_logic;
as_data : in std_logic;
as_dclk : out std_logic;
as_ncs : out std_logic;
IRDYn : out std_logic;
TRDYn : in std_logic;
FRAMEn : out std_logic;
AD : inout std_logic_vector(15 downto 0);
BEn : out std_logic_vector(1 downto 0);
INTn : in std_logic);
end component;
-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------
signal interrupts,
reset,
vbufdir,
vdtack : std_logic; -- just placeholder for irqs
signal vbufoen : std_logic_vector(1 downto 0);
signal vme_test : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- VME component instances:
-----------------------------------------------------------------------------
-- NOTE: FOR THE MOMENT THE INTERRUPT ENABLE IS DISABLED!!!!!!
reset <= not resetn;
FPGA_RESET <= reset;
VME_CONTROLLER_1: VME_CONTROLLER
port map (
reset => reset,
CLK => CLK,
--vme signals
v_am => xam,
n_v_ds => xdsn,
n_v_as => xas,
n_v_lw => xlwordn,
n_v_iackin => xiackinn,
n_v_write => xwriten,
n_v_sys_res => xsysreset,
v_dtack => vdtack,
v_berr => open,
n_v_irq => xirq,
n_v_iackout => xiackoutn,
v_ddir => vbufdir,
n_v_doe => vbufoen,
va => xaddr,
vd => xdata,
ModuleAddr => not adrsel,
--SPI signals
spi_CS => spi_CS,
SPI_SI => SPI_SI,
SPI_SO => SPI_SO,
SPI_CLK => SPI_SCK,
SPI_INT => CPU_INT,
EXT_out(8 downto 1) => C_EXT(8 downto 1),
test_out => test_lines,
--fpga config signals
fpga_nconfig => open,
fpga_nce => open,
as_asdo => open,
as_data => '0',
as_dclk => open,
as_ncs => open,
--PCI signals
IRDYn => FPGA_IRDYn,
TRDYn => FPGA_TRDYn,
FRAMEn => FPGA_FRAMEn,
AD => FPGA_AD,
BEn => FPGA_BEn,
INTn => FPGA_INTn);
--for debugging purposes - reading from OUT port (buffer type generates warnings)
xbufoen <= vbufoen;
xbufdir <= vbufdir;
xdtack <= vdtack;
CPLD_prog_nCONFIG <= 'Z';
CPLD_PROG_nCE <= 'Z';
CPLD_prog_DCLK <= 'Z';
CPLD_prog_ASDI <= 'Z';
CPLD_prog_nCS <= 'Z';
-----------------------------------------------------------------------------
-- I/O assignments:
-----------------------------------------------------------------------------
-- C_EXT(9 downto 2) <= (others => 'Z');
--C_EXT(9 downto 2) <= adrsel;
CPLD_STAT <= 'Z';
--reserved lines
-- CPLD_CLK <= 'Z'; -- 212MHz clock
RSV3 <= SPI_SI;
RSV1 <= SPI_SCK ;
--CPU_INT <= 'Z';
--RVD1 <= 'Z';
--RVD0 <= 'Z';
--RVD11 <= 'Z';
--RVD13 <= 'Z';
--RVD12 <= 'Z';
PCI_CLK <= 'Z';
Main_CK_enable <= '1';
-- test_lines(31 downto 16) <= (others => 'Z');
-- test_lines(31 downto 16)<= FPGA_AD(15 downto 0);
--test_lines(31 downto 16)<= xdata(15 downto 0);
-- test_lines(27 downto 24) <= vme_test(3 downto 0);
-- test_lines(25 downto 24) <= vbufoen ;
-- test_lines(26) <= vbufdir ;
-- test_lines(27) <= vdtack ;
-- test_lines(28) <= xwriten ;
-- test_lines(29) <= xas;
-- test_lines(31 downto 30) <= xdsn(1 downto 0);
-- test_lines(23 downto 16)<= xdata(23 downto 16);
end V1;
This diff is collapsed.
--***************************************************************************
-----------------------------------------------------------------------------
-------------- VmePackage.vhdl ----------------------------------------------
-----------------------------------------------------------------------------
--***************************************************************************
-----------------------------------------------------------------------------
--
------------------------------------------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vme is
------------------------
-- START VME INTERFACE
--
------------------------
-- selects the interrupt number the VME module
-- answer when VmeIackNA cycle is going on
subtype VmeAddressType is std_logic_vector(23 downto 1);
subtype VmeDataType is std_logic_vector(31 downto 0);
subtype ModuleAddrType is std_logic_vector(3 downto 0);
subtype ModuleAddrLType is std_logic_vector(23 downto 23 + ModuleAddrType'right - ModuleAddrType'left);
subtype SlaveAddrOutType is std_logic_vector(ModuleAddrLType'right - 1 downto 0);
subtype VmeAddresModType is std_logic_vector(5 downto 0);
subtype VmeIntLevelType is std_logic_vector(2 downto 0);
constant MODULE_ADDRESS_C : ModuleAddrLType := (23 => '1', 20 => '1', others => '0');
constant module_am : VmeAddresModType := "111001";
constant ZEROVMEADDRESS : VmeAddressType := (others => '0');
constant ONEVMEADDRESS : VmeAddressType := (ZEROVMEADDRESS'right => '1', others => '0');
constant STDNONPRIVPROGACC : VmeAddresModType := "111001";
type VmeCellType is
record
Address : VmeAddressType;
Data : VmeDataType;
Am : VmeAddresModType;
end record VmeCellType;
type VmeAddAmType is
record
Address : VmeAddressType;
Am : VmeAddresModType;
end record VmeAddAmType;
type IntAddDataType is
record
Address : integer;
Data : VmeDataType;
end record IntAddDataType;
type VmeBusOutRecord is
record
-- clk : std_logic;
VmeAddrA : VmeAddressType;
VmeAsNA : std_logic;
VmeAmA : VmeAddresModType;
VmeDs1NA : std_logic;
VmeDs0NA : std_logic;
VmeLwordNA: std_logic;
VmeWriteNA : std_logic;
VmeIackNA : std_logic;
IackInNA : std_logic;
-- ModuleAddr : std_logic_vector(4 downto 0);
-- DataFromMemValid : std_logic;
-- DataFromMem: VmeDataType;
-- data_writen_valid : std_logic;
-- ResetNA : std_logic;
-- UserIntReqN : std_logic;
-- UserBlocks : std_logic;
VmeData : VmeDataType;
writeFinished : boolean;
readFinished : boolean;
takeControl : boolean;
end record VmeBusOutRecord;
type VmeBusOutRecordArray is array (natural range <>) of VmeBusOutRecord;
type VmeBusInRecord is
record
VmeData : VmeDataType;
VmeDir : std_logic;
VmeBufOeN : std_logic;
IackOutNA: std_logic;
VmeAsNA : std_logic;
VmeIntReqN : std_logic_vector(7 downto 0);
dtack_n : std_logic;
end record VmeBusInRecord;
--type StdLogVecArray is array (natural range <>) of Std_logic_vector;
-- Interrupt vector to be put on data bus during
-- the VME interrupt cycle
function PullUpStdLogVec(input1, input2 : Std_logic_vector) return Std_logic_vector;
function PullUpStdLog(input1, input2 : Std_logic) return Std_logic ;
function PullUpVmeBusOut(inputs : VmeBusOutRecordArray) return VmeBusOutRecord;
--function PullUpStdLog (inputs : std_logic_vector) return
end;
package body vme is
function PullUpStdLogVec(input1, input2 : Std_logic_vector) return Std_logic_vector is
variable vStdLogVec : Std_logic_vector(31 downto 0);
begin
vStdLogVec := (others => 'U');
for M in input2'range loop
case input2(M) is
when 'U' |'X' | 'W' => if input1(M) = '0' or input1(M) = 'L' then
vStdLogVec(M) := '0';
end if;
-- when 'X' => vStdLog := 'U';
when '0' => vStdLogVec(M) := '0';
when '1' => vStdLogVec(M) := input1(M);
when 'Z' => vStdLogVec(M) := input1(M);
-- when 'W' => vStdLogVec(M) := 'U';
when 'L' => vStdLogVec(M) := '0';
when 'H' => vStdLogVec(M) := input1(M);
when others => null;
end case;
end loop;
return vStdLogVec(input2'range);
end;
function PullUpStdLog(input1, input2 : Std_logic) return Std_logic is
variable vStdLog : Std_logic;
begin
vStdLog := 'U';
case input2 is
when 'U' |'X' | 'W' => if input1 = '0' or input1 = 'L' then
vStdLog := '0';
end if;
-- when 'X' => vStdLog := 'U';
when '0' => vStdLog := '0';
when '1' => vStdLog := input1;
when 'Z' => vStdLog := input1;
-- when 'W' => vStdLog := 'U';
when 'L' => vStdLog := '0';
when 'H' => vStdLog := input1;
-- when '-' => vStdLog := 'U';
when others => null;
end case;
return vStdLog;
end;
function PullUpVmeBusOut(inputs : VmeBusOutRecordArray) return VmeBusOutRecord is
variable vVmeBusOut : VmeBusOutRecord;
begin
vVmeBusOut.VmeAddrA := (others => '1');
vVmeBusOut.VmeAsNA := '1';
vVmeBusOut.VmeAmA := (others => '1');
vVmeBusOut.VmeDs1NA := '1';
vVmeBusOut.VmeDs0NA := '1';
vVmeBusOut.VmeLwordNA:= '1';
vVmeBusOut.VmeWriteNA := '1';
vVmeBusOut.VmeIackNA := '1';
vVmeBusOut.IackInNA := '1';
vVmeBusOut.VmeData := (others => 'Z');
vVmeBusOut.writeFinished := false;
vVmeBusOut.readFinished := false;
for I in inputs'range loop
if inputs(I).takeControl then
vVmeBusOut.VmeAddrA := inputs(I).VmeAddrA;
vVmeBusOut.VmeAsNA := inputs(I).VmeAsNA ;
vVmeBusOut.VmeAmA := inputs(I).VmeAmA;
vVmeBusOut.VmeDs1NA := inputs(I).VmeDs1NA ;
vVmeBusOut.VmeDs0NA := inputs(I).VmeDs0NA ;
vVmeBusOut.VmeLwordNA:= inputs(I).VmeLwordNA;
vVmeBusOut.VmeWriteNA := inputs(I).VmeWriteNA ;
vVmeBusOut.VmeIackNA := inputs(I).VmeIackNA ;
vVmeBusOut.IackInNA := inputs(I).IackInNA ;
vVmeBusOut.VmeData := inputs(I).VmeData ;
vVmeBusOut.writeFinished := inputs(I).writeFinished;
vVmeBusOut.readFinished := inputs(I).readFinished;
end if;
end loop;
return vVmeBusOut;
end;
end;
This diff is collapsed.
This diff is collapsed.
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: DPRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY DPRAM IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END DPRAM;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 8192,
numwords_b => 4096,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 13,
widthad_b => 12,
width_a => 16,
width_b => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL rdaddress[11..0]
-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL wraddress[12..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
-- Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
This diff is collapsed.
This diff is collapsed.
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: SPRAM1kx32.vhd
-- Megafunction Name(s):
-- altsyncram
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SPRAM1kx32 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END SPRAM1kx32;
ARCHITECTURE SYN OF spram1kx32 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32_inst.vhd TRUE
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clkdivider is
generic (
divider : integer := 50); -- number of clocks to generate enable pulse
port (
clk : in std_logic; -- general clock
reset : in std_logic; -- async reset
clkenable : out std_logic); -- clock enable used to turn on the clock
end clkdivider;
architecture v1 of clkdivider is
begin -- v1
-- purpose: counts down to zero and when at zero, then it generates clkenable pulse which is exactly 1 tick lock
-- type : sequential
-- inputs : clk, reset
count: process (clk, reset)
variable counter : integer range divider downto 0;
-- counter stuff
begin -- process count
if reset = '1' then -- asynchronous reset (active high)
counter := divider; -- set the state to the divider val.
elsif clk'event and clk = '1' then -- rising clock edge
counter := counter - 1; -- decrease counts
if counter = 0 then
counter := divider;
clkenable <= '1';
else
clkenable <= '0';
end if;
end if;
end process count;
end v1;
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram_32x32.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.1 Build 156 04/30/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram_32x32 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dpram_32x32;
ARCHITECTURE SYN OF dpram_32x32 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 5,
widthad_b => 5,
width_a => 32,
width_b => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0]
-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment