project: added build flow.

54a0d9ca · John Gill · eaa7b13d · 54a0d9ca · 54a0d9ca · 54a0d9ca
Commit 54a0d9ca authored Nov 28, 2019 by John Gill
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.gitignore hdl/syn/.gitignore +7 -0

README hdl/syn/README +13 -0

wr2rf_vme.tcl hdl/syn/wr2rf_vme.tcl +62 -0

wr2rf_vme.xdc hdl/syn/wr2rf_vme.xdc +1 -0

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--- a/hdl/syn/.gitignore
+++ b/hdl/syn/.gitignore
+*.log
+*.jou
+Makefile
+*.tcl
+vivado*.backup.*
+project
+wr2rf_vme.*
\ No newline at end of file
--- a/hdl/syn/README
+++ b/hdl/syn/README
+To generate the wr2rf_vme fpga design, you must:
+
+- run hdlmake in the current syn directory to generate a list of file
+  dependencies - specifically - files.tcl
+
+  
+  $ hdlmake
+
+- run vivado to progress through the build phases (synth, opt, place, phys_opt
+  and route).
+
+  $ vivado -mode tcl -source wr2rf_vme.tcl
+
--- a/hdl/syn/wr2rf_vme.tcl
+++ b/hdl/syn/wr2rf_vme.tcl
+set projDir [file dirname [info script]]
+
+# Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
+set speed   2
+set kintex7 xc7k70tfbg676-${speed}
+set device  ${kintex7}
+
+set top     wr2rf_vme
+
+# Check hdlmake has generated file dependencies
+if {![file exists files.tcl]} {
+    puts "File: files.tcl not found, please check hdlmake has generated the file dependencies."
+    exit 1
+}
+
+source files.tcl
+#read_vhdl $projDir/XXX.vhd
+
+# constraint files
+read_xdc $projDir/${top}.xdc
+
+set start_time [clock seconds]
+
+synth_design -top ${top} -part ${device} > ${top}_synth.log
+write_checkpoint -force ${top}_synth
+
+opt_design -directive Explore -verbose > ${top}_opt.log
+write_checkpoint -force ${top}_opt
+
+place_design -directive Explore > ${top}_place.log
+write_checkpoint -force ${projDir}/${top}_place
+
+phys_opt_design -directive Explore > ${top}_phys_opt.log
+write_checkpoint -force ${projDir}/${top}_phys_opt
+
+route_design -directive Explore > ${top}_route.log
+write_checkpoint -force ${projDir}/${top}_route
+
+report_timing_summary -file ${top}_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type full -file ${top}_timing.rpt
+report_utilization -hierarchical -file ${top}_utilization.rpt
+report_io -file ${top}_pin.rpt
+
+# bitstream configuration...
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property CFGBVS GND [current_design]
+#set_property CONFIG_MODE SPIx8 [current_design]
+#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
+#set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-2 [current_design]
+#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+write_bitstream -force ${projDir}/${top}.bit
+#write_cfgmem -force -format mcs -interface spix8 -size 32 -loadbit "up 0x0 pcieg2_kcu105.bit" pcieg2_kcu105.mcs
+
+
+
+set end_time [clock seconds]
+set total_time [ expr { $end_time - $start_time} ]
+set absolute_time [clock format $total_time -format {%H:%M:%S} -gmt true ]
+puts "\ntotal build time: $absolute_time\n"
+
+exit 0
--- a/hdl/syn/wr2rf_vme.xdc
+++ b/hdl/syn/wr2rf_vme.xdc
+# Put constraints in the syn tree.