Rename file, add VME ports.

c89720a1 · Tristan Gingold · a6cc2cf1 · c89720a1
Commit c89720a1 authored Oct 25, 2019 by Tristan Gingold
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wr2rf_vme.vhd hdl/rtl/wr2rf_vme.vhd +65 -0

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--- a/hdl/rtl/wr2rf_vme_core.vhd
+++ b/hdl/rtl/wr2rf_vme_core.vhd
@@ -26,9 +26,40 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

-entity wr2rf_vme_core is
-end wr2rf_vme_core;
+entity wr2rf_vme is
+  port (
+    ---------------------------------------------------------------------------
+    -- VME interface D16 A24
+    -- Note: retry, berr not required
+    --       addr is input only.
+    ---------------------------------------------------------------------------

-architecture rtl of wr2rf_vme_core is
+    vme_write_n_i    : in    std_logic;
+    vme_sysreset_n_i : in    std_logic;
+    vme_retry_oe_o   : out   std_logic;
+    vme_retry_n_o    : out   std_logic;
+    vme_lword_n_i    : in    std_logic;
+    vme_iackout_n_o  : out   std_logic;
+    vme_iackin_n_i   : in    std_logic;
+    vme_iack_n_i     : in    std_logic;
+    vme_dtack_oe_o   : out   std_logic;
+    vme_dtack_n_o    : out   std_logic;
+    vme_ds_n_i       : in    std_logic_vector(1 downto 0);
+    vme_data_oe_n_o  : out   std_logic;
+    vme_data_dir_o   : out   std_logic;
+    vme_berr_o       : out   std_logic;
+    vme_as_n_i       : in    std_logic;
+    vme_irq_o        : out   std_logic_vector(7 downto 1);
+    vme_data_b       : inout std_logic_vector(15 downto 0);
+    vme_am_i         : in    std_logic_vector(5 downto 0);
+    vme_addr_i       : in    std_logic_vector(23 downto 1);
+
+    --  Geographic address
+    vme_gap_i        : in    std_logic;
+    vme_ga_i         : in    std_logic_vector(4 downto 0)
+  );
+end wr2rf_vme;
+
+architecture rtl of wr2rf_vme is
 begin
 end rtl;