-- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+

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-- Title         : FIFO with depth one word
-- Project       : 
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-- File          : z126_01_fifo_d1.vhd
-- Author        : Andreas Geissler
-- Email         : Andreas.Geissler@men.de
-- Organization  : MEN Mikro Elektronik Nuremberg GmbH
-- Created       : 03/02/14
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-- Simulator     : ModelSim-Altera PE 6.4c
-- Synthesis     : Quartus II 12.1 SP2
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-- Description :
--
-- This module describes a fifo with depth one word.
-- No EAB-Block is required, just registers.
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-- Hierarchy:
--
-- 
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--
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--                         History                                    
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-- $Revision: 1.1 $
--
-- $Log: z126_01_fifo_d1.vhd,v $
-- Revision 1.1  2014/03/03 17:49:40  AGeissler
-- Initial Revision
--
--
--
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY z126_01_fifo_d1 IS
   GENERIC (
      width    : IN integer:=8 );
   PORT (
      rstn     : IN std_logic;
         
      clk_a    : IN std_logic;
      wr_a     : IN std_logic;
      data_a   : IN std_logic_vector(width-1 DOWNTO 0);
      full_a   : OUT std_logic;
      
      clk_b    : IN std_logic;
      rd_b     : IN std_logic;
      data_b   : OUT std_logic_vector(width-1 DOWNTO 0);
      full_b   : OUT std_logic
   );
END z126_01_fifo_d1;

ARCHITECTURE z126_01_fifo_d1_arch OF z126_01_fifo_d1 IS 
   SIGNAL wr_ptr        : std_logic;
   SIGNAL rd_ptr        : std_logic;
   SIGNAL wr_ptr_b      : std_logic;
   SIGNAL rd_ptr_a      : std_logic;
   SIGNAL full_a_int    : std_logic;   
   SIGNAL full_b_int    : std_logic;   
   SIGNAL data_a_q      : std_logic_vector(width-1 DOWNTO 0);
BEGIN
   full_a_int <= '1' WHEN (wr_ptr = '1' AND rd_ptr_a = '0') OR (wr_ptr = '0' AND rd_ptr_a = '1') ELSE '0';
   full_a <= full_a_int;
   full_b_int <= '1' WHEN (wr_ptr_b = '1' AND rd_ptr = '0') OR (wr_ptr_b = '0' AND rd_ptr = '1') ELSE '0';
   full_b <= full_b_int;
   
   proca : PROCESS (clk_a, rstn)
   BEGIN
      IF rstn = '0' THEN
         data_a_q <= (OTHERS => '0');
         wr_ptr <= '0';
         rd_ptr_a <= '0';
      ELSIF clk_a'EVENT AND clk_a = '1' THEN
         rd_ptr_a <= rd_ptr;
         IF wr_a = '1' AND full_a_int = '0' THEN
            data_a_q <= data_a;
            wr_ptr <= NOT wr_ptr;
         END IF;
      END IF;
   END PROCESS proca;
   
   procb : PROCESS (clk_b, rstn)
   BEGIN
      IF rstn = '0' THEN
         data_b <= (OTHERS => '0');
         rd_ptr <= '0';
         wr_ptr_b <= '0';
      ELSIF clk_b'EVENT AND clk_b = '1' THEN
         wr_ptr_b <= wr_ptr;
         IF rd_b = '1' AND full_b_int = '1' THEN 
            data_b <= data_a_q;
            rd_ptr <= NOT rd_ptr;
         END IF;
      END IF;
   END PROCESS procb;
   
END z126_01_fifo_d1_arch;
