.. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+

16z091-01 IP core, Wishbone to PCIe bridge
==========================================

General description
-------------------

This IP core implements a Wishbone to PCIe bridge. The Wishbone interface is
32bit, the PCIe side allows x1, x2 and x4 configurations. Details concerning the
architecture of this IP core can be found in

    inStep -> _MAIN -> 16Z091-/16Z091-01/Specifications/work/16Z091-01_IcArchSpec.doc

Integration advice
------------------

+------------------+
| Generic settings |
+------------------+
Some of the generics remain constant for all MEN devices. Thus their default value should be used:
   VENDOR_ID            : natural                       := 16#1A88#;
   DEVICE_ID            : natural                       := 16#4D45#;
   REVISION_ID          : natural                       := 16#0#;
   CLASS_CODE           : natural                       := 16#068000#;
   SUBSYSTEM_DEVICE_ID  : natural                       := 16#5A91#;


Other generics can be adapted to the special needs of each top level design:
   generics with restricted values:
   --------------------------------
   SIMULATION           : std_logic                     := '0';
      possible values:
      =1 := simulation
      =0 := synthesis 
   FPGA_FAMILY          : family_type                   := NONE;
      possible values: CYCLONE4, CYCLONE5

   USE_LANES            : std_logic_vector(2 downto 0)  := "001";            
      possible values:
      ="001" := 1 lane
      ="010" := 2 lanes
      ="100" := 4 lanes

   SUBSYSTEM_VENDOR_ID  : natural                       := 16#9B#;
      possible values according to FPGA_overview.xls

   PCIE_REQUEST_LENGTH  : std_logic_vector(9 downto 0)  := "0000010000";    -- 16DW = 64Byte
      typical values: 
      ="0000010000" := 16DW = 64Byte
      ="0000100000" := 32DW = 128Byte


   generics with any value within given range:
   -------------------------------------------
   IRQ_WIDTH            : integer range 32 downto 1     := 1;

   NR_OF_WB_SLAVES      : natural range 63 DOWNTO 1     := 12;

   BAR management - define how many BARs are used, if they are memory or I/O mapped and which size they have.
   The minimum address range requested is 128 bytes.
   Settings for BAR_MASK:
      31 downto 7 := base address, configure the desired size with '0'
       6 downto 4 := RESERVED
       3          := prefetchable, set to '1' if prefetchable, otherwise '0'
       2 downto 1 := type, must be "00" to denote 32bit encoder
       0          := memory space indicator, =0 for memory, =1 for I/O
      
   Examples: 
      BAR_MASK_x <= x"FFFFF000"    => default setting for unused BARs
      BAR_MASK_x <= x"FFF00000"    => Size of BAR is 1MB, memory mapped
      BAR_MASK_x <= x"FFFC0001"    => Size of BAR is 256kB, IO mapped
      BAR_MASK_x <= x"FF800008"    => Size of BAR is 8MB, memory mapped, prefechable
      BAR_MASK_x <= x"FFFFF000"    => Size of BAR is 4kB, memory mapped, smallest size for memory mapping
      BAR_MASK_x <= x"FFFFFF01"    => Size of BAR is 256B, memory mapped, largest size of IO mapping
      BAR_MASK_x <= x"FFFFFFFD"    => Size of BAR is 4B, memory mapped, smallest size of IO mapping
      

   NR_OF_BARS_USED      : natural range 6 downto 1      := 5;
   BAR_MASK_0           : std_logic_vector(31 downto 0) := x"FF000008";
   BAR_MASK_1           : std_logic_vector(31 downto 0) := x"FF000008";
   BAR_MASK_2           : std_logic_vector(31 downto 0) := x"FF000000";
   BAR_MASK_3           : std_logic_vector(31 downto 0) := x"FF000000";
   BAR_MASK_4           : std_logic_vector(31 downto 0) := x"FF000001";
   BAR_MASK_5           : std_logic_vector(31 downto 0) := x"FF000001";
   ROM_MASK             : std_logic_vector(31 downto 0) := x"FFFF0000";

   Manage internal FIFO widths for RX and TX FIFOs:
   RX_LPM_WIDTHU        : integer range 10 DOWNTO 5     := 10; -- RX FIFO
   TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5     := 5;  -- TX FIFO for header information
   TX_DATA_LPM_WIDTHU   : integer range 10 DOWNTO 5     := 10; -- TX FIFO for user data


   generic for debugging:
   ----------------------
   GP_DEBUG_PORT_WIDTH  : positive := 1


+-------------------+
| Cyclone V support |
+-------------------+
Cyclone V support is added to the 16z091-01 top file using a new architecture. Therefore you specify it
using configurations just as described above.

Example:
configuration ip_16z091_01_top_cfg of ip_16z091_01_top is
  --for ip_16z091_01_top_arch       <-- use this for Cyclone IV
  for ip_16z091_01_top_cycv_arch    <-- use this for Cyclone V
    for ip_16z091_01_comp : ip_16z091_01
      use configuration work.ip_16z091_01_cfg;  
    end for;
  end for;
end configuration ip_16z091_01_top_cfg;
   
+------------+
| Simulation |
+------------+
* add fpga_pkg_2:
      ../../16z000-/Source/fpga_pkg_2.vhd

* first of all add the special simulation sources for the hard IP to your compile script:
  for Cyclone IV add
      ../Source/x1/Simulation/altpcie_rs_serdes.vhd \
      ../Source/x1/Simulation/altpcie_pll_100_250.vhd \
      ../Source/x1/Simulation/altpcie_pll_125_250.vhd \
      ../Source/x1/Simulation/Hard_IP_x1_core.vho

   for Cyclone V add
      vlog -work work \
             ../Source/CycV/altpcie_cv_hip_ast_hwtcl.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_rs_serdes.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_rs_serdes.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_rs_hip.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_rs_hip.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_av_hip_128bit_atom.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_av_hip_128bit_atom.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_av_hip_ast_hwtcl.v \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_av_hip_ast_hwtcl.v \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altera_xcvr_functions.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altera_xcvr_functions.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_to_xcvr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_to_ip.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_merger.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_to_xcvr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_to_ip.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_merger.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_avmm_csr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_tx_pma_ch.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_tx_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_rx_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pcs_ch.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pcs.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_avmm.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_native.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_plls.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_data_adapter.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_reconfig_bundle_to_basic.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_reconfig_bundle_to_xcvr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_avmm_csr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_tx_pma_ch.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_tx_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_rx_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pma.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pcs_ch.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pcs.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_avmm.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_native.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_plls.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_data_adapter.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_reconfig_bundle_to_basic.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_reconfig_bundle_to_xcvr.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_8g_rx_pcs_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_8g_tx_pcs_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_common_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_common_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_pipe_gen1_2_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_rx_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_rx_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_tx_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_tx_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_8g_rx_pcs_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_8g_tx_pcs_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_common_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_common_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_pipe_gen1_2_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_rx_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_rx_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_tx_pcs_pma_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_tx_pld_pcs_interface_rbc.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_reset_ctrl_lego.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_reset_ctrl_tgx_cdrauto.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_resync.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_reset_ctrl_lego.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_reset_ctrl_tgx_cdrauto.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_resync.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_common_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_common.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_pcs8g_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_pcs8g.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_selector.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_mgmt2dec.sv \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altera_wait_generate.v \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_common_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_common.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_pcs8g_h.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_pcs8g.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_selector.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_mgmt2dec.sv \
             ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altera_wait_generate.v \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_emsip_adapter.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_pipe_native_hip.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_emsip_adapter.sv \
         -sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_pipe_native_hip.sv

      vcom -work work ../Source/CycV/PCIeHardIPCycV.vhd

      #------------------------------------
      # compile files for reconfig module
      #------------------------------------
      vcom -work work ../Source/CycV/CycVTransReconf.vhd

* below the special files add all 16z091-01 sources to your compile script according to
  the following list:
      ../Source/src_utils_pkg.vhd \
      ../Source/alt_reconf.vhd \
      ../Source/rx_fifo.vhd \
      ../Source/tx_data_fifo.vhd \
      ../Source/tx_header_fifo.vhd \
      ../Source/err_fifo.vhd \
      ../Source/rx_len_cntr.vhd \
      ../Source/rx_get_data.vhd \
      ../Source/rx_ctrl.vhd \
      ../Source/rx_module.vhd \
      ../Source/z091_01_wb_master.vhd \
      ../Source/error.vhd \
      ../Source/tx_put_data.vhd \
      ../Source/tx_compl_timeout.vhd \
      ../Source/tx_ctrl.vhd \
      ../Source/tx_module.vhd \
      ../Source/init.vhd \
      ../Source/z091_01_wb_slave.vhd \
      ../Source/interrupt_core.vhd \
      ../Source/interrupt_wb.vhd \
      ../Source/ip_16z091_01.vhd \
      ../Source/z091_01_wb_adr_dec.vhd \    <-- change this line to your top-level source folder and your version of the z091_01_wb_adr_dec
      ../Source/x1/Hard_IP_x1_serdes.vhd \
      ../Source/x1/Hard_IP_x1.vhd \
      ../Source/ip_16z091_01_top.vhd



+-----------+
| Synthesis |
+-----------+
* add the package files to your *.qsf file:
      set_global_assignment -name VHDL_FILE "../../16z000-/Source/fpga_pkg_2.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/src_utils_pkg.vhd"

* add special Veriolog files that are needed for the hard IP:
  for Cyclone IV add
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/alt_reconf.vhd"
      set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/pciexp_dcram.v"
      set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"
      set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v"

  for Cyclone V add (as well described in z091_01_syn_con_cyc5.tcl)
      set_global_assignment -name VHDL_FILE "../../../16z091-01/Source/CycV/PCIeHardIPCycV.vhd" -library PCIeHardIPCycV
      set_global_assignment -name VHDL_FILE "../../../16z091-01/Source/CycV/CycVTransReconf.vhd" -library CycVTransReconf
      set_global_assignment -name QIP_FILE "../../../16z091-01/Source/CycV/PCIeHardIPCycV.qip"
      set_global_assignment -name QIP_FILE "../../../16z091-01/Source/CycV/CycVTransReconf.qip"

* add the 16z091-01 source files to your *.qsf file:
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1_serdes.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1_core.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_adr_dec.vhd"  <-- change this line to your top-level 
                                                                                  source folder and your version of the
                                                                                  z091_01_wb_adr_dec
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_slave.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_master.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_put_data.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_header_fifo.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_data_fifo.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_compl_timeout.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_ctrl.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_module.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_len_cntr.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_fifo.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_get_data.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_ctrl.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_module.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/interrupt_wb.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/interrupt_core.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/init.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/err_fifo.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/error.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/ip_16z091_01.vhd"
      set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/ip_16z091_01_top.vhd"

* add the 16z091-01 timing constraints to your *.sdc file:
  for Cyclone IV add
      set_global_assignment -name SDC_FILE z91_01_tmg_con.sdc

  for Cyclone V add
      set_global_assignment -name SDC_FILE z91_01_tmg_con_cyc5.sdc
  => files are located in /16z091-01/Synthesis

