-- SPDX-FileCopyrightText: 2017, CERN
-- SPDX-License-Identifier: CERN-OHL-S-2.0+

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-- Title       : Generic Altera Fifo
-- Project     : PCIe-to-VME bridge
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-- File        : generic_dcfifo_mixedw.vhd
-- Author      : Grzegorz Daniluk
-- Email       : grzegorz.daniluk@cern.ch
-- Organization: CERN
-- Created     : 17/05/2017
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-- Description : 
-- Generic, parametrized mixed width fifo based on Altera dcfifo.
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--
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library ieee;
use ieee.std_logic_1164.all;

entity generic_dcfifo_mixedw is
  generic (
    g_device_family : string  := "Cyclone IV GX";
    g_fifo_depth    : natural := 32;
    g_data_width    : natural := 32;
    g_data_widthu   : natural := 5;
    g_q_width       : natural := 64;
    g_q_widthu      : natural := 4;
    g_showahead     : string  := "OFF");
  port (
    aclr    : in  std_logic := '0';
    data    : in  std_logic_vector (g_data_width-1 downto 0);
    rdclk   : in  std_logic ;
    rdreq   : in  std_logic ;
    wrclk   : in  std_logic ;
    wrreq   : in  std_logic ;
    q       : out std_logic_vector (g_q_width-1 downto 0);
    rdempty : out std_logic ;
    wrfull  : out std_logic ;
    wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end generic_dcfifo_mixedw;

architecture syn of generic_dcfifo_mixedw is
  signal rst_n_a : std_logic;
begin
  rst_n_a <= not aclr;
  inst_fifo: entity work.generic_async_fifo_mixedw
  generic map (
    g_wr_width => g_data_width,
    g_rd_width => g_q_width,
    g_size => g_fifo_depth,
    g_show_ahead => g_showahead = "ON",
    g_memory_implementation_hint => open
  )
  port map (
    rst_n_a_i => rst_n_a,
    clk_wr_i => wrclk,
    d_i => data,
    we_i => wrreq,
    wr_full_o => wrfull,
    wr_count_o => wrusedw,
    clk_rd_i => rdclk,
    q_o => q,
    rd_i => rdreq,
    rd_empty_o => rdempty,
    rd_count_o => open
  );
end syn;
