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Contents of this folder
=======================

``16z000-00_src``: VHDL package for technology definitions.

``16z024-01_src``: VHDL source for FPGA internal ROM (used for storing the Chameleon table).

``16z091-01_src``: VHDL source and Altera IP cores for PCIe to Wisbhone interface.

``16z100-01_src``: VHDL source for Wishbone interconnect.

``16z126-01_src``: VHDL source and Altera IP cores for serial flash remote update.

``syn``: Altera Quartus synthesis (including top-level HDLmake manifest).

``testbench``: HDL simulation testbench (more info in README inside folder).

``top``: VHDL top-level module, Altera PCIe PLL IP core, peripherals and Chameleon table.

