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VME64x core
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VME64x core
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05081240
Commit
05081240
authored
Nov 14, 2017
by
Tristan Gingold
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Add README, adjust Manifest.py
parent
dc69f930
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README
README
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Manifest.py
hdl/testbench/simple_tb/Manifest.py
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README
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05081240
VME64x Core
===========
Running the testbench
---------------------
After having cloned the repository, simply do:
git submodule init
git submodule update
cd hdl/testbench/simple_tb/modelsim
hdlmake
make
sh run_all.sh
This is an automatic testbench with a yes/no status.
It runs the testbench several times with a different scenario value.
The last line should be: OK!
Tested with ModelSim SE-64 10.2a on linux.
hdl/testbench/simple_tb/Manifest.py
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05081240
...
@@ -3,6 +3,5 @@ files = [
...
@@ -3,6 +3,5 @@ files = [
]
]
modules
=
{
modules
=
{
"local"
:
[
"../../rtl"
],
"local"
:
[
"../../rtl"
,
"../../ip_cores/general-cores"
],
"git"
:
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
}
}
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