Commit 07c2a3ef authored by Tristan Gingold's avatar Tristan Gingold

Remove g_NBR_DECODER.

parent 6ce9cc00
...@@ -27,7 +27,6 @@ entity vme64x_core is ...@@ -27,7 +27,6 @@ entity vme64x_core is
g_end_user_csr : std_logic_vector(23 downto 0); g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0); g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0); g_end_sn : std_logic_vector(23 downto 0);
g_nbr_decoders : natural range 1 to 8;
g_decoder_0_adem : std_logic_vector(31 downto 0); g_decoder_0_adem : std_logic_vector(31 downto 0);
g_decoder_0_amcap : std_logic_vector(63 downto 0); g_decoder_0_amcap : std_logic_vector(63 downto 0);
g_decoder_0_dawpr : std_logic_vector(7 downto 0); g_decoder_0_dawpr : std_logic_vector(7 downto 0);
...@@ -124,7 +123,6 @@ begin ...@@ -124,7 +123,6 @@ begin
g_end_user_csr => g_end_user_csr, g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn, g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn, g_end_sn => g_end_sn,
g_nbr_decoders => g_nbr_decoders,
g_decoder(0).adem => g_decoder_0_adem, g_decoder(0).adem => g_decoder_0_adem,
g_decoder(0).amcap => g_decoder_0_amcap, g_decoder(0).amcap => g_decoder_0_amcap,
g_decoder(0).dawpr => g_decoder_0_dawpr, g_decoder(0).dawpr => g_decoder_0_dawpr,
......
...@@ -206,7 +206,6 @@ package vme64x_pkg is ...@@ -206,7 +206,6 @@ package vme64x_pkg is
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000"; g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_NBR_DECODERS : natural range 1 to 8 := 2;
g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default); g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
......
...@@ -156,8 +156,7 @@ entity xvme64x_core is ...@@ -156,8 +156,7 @@ entity xvme64x_core is
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000"; g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
-- Number of function decoder implemented and decoder parameters. -- Function decoder parameters.
g_NBR_DECODERS : natural range 1 to 8 := 2;
g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default); g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default);
port ( port (
-- Main clock and reset. -- Main clock and reset.
......
...@@ -280,7 +280,6 @@ begin ...@@ -280,7 +280,6 @@ begin
g_BEG_SN => x"000000", g_BEG_SN => x"000000",
g_END_SN => x"000000", g_END_SN => x"000000",
g_NBR_DECODERS => 2,
g_decoder_0_adem => x"ff000000", g_decoder_0_adem => x"ff000000",
g_decoder_0_amcap => x"00000000_0000ff00", g_decoder_0_amcap => x"00000000_0000ff00",
g_decoder_0_dawpr => x"84", g_decoder_0_dawpr => x"84",
......
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