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VME64x core
Commits
173dd4e4
Commit
173dd4e4
authored
Oct 11, 2017
by
Tristan Gingold
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Plain Diff
Remove unused declarations.
parent
fbde2002
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5 changed files
with
12 additions
and
35 deletions
+12
-35
VME64xCore_Top.vhd
hdl/rtl/VME64xCore_Top.vhd
+0
-3
VME_CR_CSR_Space.vhd
hdl/rtl/VME_CR_CSR_Space.vhd
+0
-12
VME_User_CSR.vhd
hdl/rtl/VME_User_CSR.vhd
+8
-10
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+1
-0
top_tb.vhd
hdl/sim/simple_tb/top_tb.vhd
+3
-10
No files found.
hdl/rtl/VME64xCore_Top.vhd
View file @
173dd4e4
...
...
@@ -567,9 +567,6 @@ begin
-- User CSR space
gen_int_user_csr
:
if
g_USER_CSR_EXT
=
false
generate
Inst_VME_User_CSR
:
entity
work
.
VME_User_CSR
generic
map
(
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
s_reset_n
,
...
...
hdl/rtl/VME_CR_CSR_Space.vhd
View file @
173dd4e4
...
...
@@ -219,15 +219,6 @@ architecture rtl of VME_CR_CSR_Space is
constant
c_BEG_CRAM
:
crcsr_addr
:
=
unsigned
(
g_BEG_CRAM
(
18
downto
2
));
constant
c_END_CRAM
:
crcsr_addr
:
=
unsigned
(
g_END_CRAM
(
18
downto
2
));
constant
c_BAR_REG
:
integer
:
=
16
#
7
ffff
#
/
4
;
constant
c_BIT_SET_REG
:
integer
:
=
16
#
7
fffb
#
/
4
;
constant
c_BIT_CLR_REG
:
integer
:
=
16
#
7
fff7
#
/
4
;
constant
c_CRAM_OWNER_REG
:
integer
:
=
16
#
7
fff3
#
/
4
;
constant
c_USR_SET_REG
:
integer
:
=
16
#
7
ffef
#
/
4
;
constant
c_USR_CLR_REG
:
integer
:
=
16
#
7
ffeb
#
/
4
;
constant
c_ADER_REG_END
:
integer
:
=
16
#
7
ffdf
#
/
4
;
constant
c_ADER_REG_BEG
:
integer
:
=
16
#
7
ff63
#
/
4
;
-- Indexes in bit set/clr register
constant
c_RESET_BIT
:
integer
:
=
7
;
constant
c_SYSFAIL_EN_BIT
:
integer
:
=
6
;
...
...
@@ -471,9 +462,6 @@ begin
variable
csr_idx
:
unsigned
(
7
downto
4
);
variable
csr_boff
:
unsigned
(
3
downto
2
);
variable
v_addr
:
unsigned
(
18
downto
2
);
variable
v_index
:
integer
;
variable
v_byte
:
integer
;
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
...
...
hdl/rtl/VME_User_CSR.vhd
View file @
173dd4e4
...
...
@@ -59,9 +59,6 @@ use ieee.numeric_std.all;
use
work
.
vme64x_pack
.
all
;
entity
VME_User_CSR
is
generic
(
g_WB_DATA_WIDTH
:
integer
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -88,13 +85,14 @@ architecture rtl of VME_User_CSR is
constant
c_IRQ_VECTOR
:
integer
:
=
16
#
0002
f
#
/
4
;
constant
c_IRQ_LEVEL
:
integer
:
=
16
#
0002
b
#
/
4
;
constant
c_ENDIAN
:
integer
:
=
16
#
00023
#
/
4
;
constant
c_TIME0_NS
:
integer
:
=
16
#
0001
f
#
/
4
;
constant
c_TIME1_NS
:
integer
:
=
16
#
0001
b
#
/
4
;
constant
c_TIME2_NS
:
integer
:
=
16
#
00017
#
/
4
;
constant
c_TIME3_NS
:
integer
:
=
16
#
00013
#
/
4
;
constant
c_TIME4_NS
:
integer
:
=
16
#
0000
f
#
/
4
;
constant
c_BYTES0
:
integer
:
=
16
#
0000
b
#
/
4
;
constant
c_BYTES1
:
integer
:
=
16
#
00007
#
/
4
;
-- Now unused.
-- constant c_TIME0_NS : integer := 16#0001f# / 4;
-- constant c_TIME1_NS : integer := 16#0001b# / 4;
-- constant c_TIME2_NS : integer := 16#00017# / 4;
-- constant c_TIME3_NS : integer := 16#00013# / 4;
-- constant c_TIME4_NS : integer := 16#0000f# / 4;
-- constant c_BYTES0 : integer := 16#0000b# / 4;
-- constant c_BYTES1 : integer := 16#00007# / 4;
constant
c_WB32BITS
:
integer
:
=
16
#
00003
#
/
4
;
begin
...
...
hdl/rtl/xvme64x_core.vhd
View file @
173dd4e4
...
...
@@ -159,6 +159,7 @@ begin -- wrapper
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
,
g_USER_CSR_EXT
=>
g_USER_CSR_EXT
,
g_MANUFACTURER_ID
=>
g_MANUFACTURER_ID
,
g_BOARD_ID
=>
g_BOARD_ID
,
g_REVISION_ID
=>
g_REVISION_ID
,
...
...
hdl/sim/simple_tb/top_tb.vhd
View file @
173dd4e4
...
...
@@ -47,7 +47,6 @@ architecture behaviour of top_tb is
subtype
lword_t
is
std_logic_vector
(
31
downto
0
);
subtype
qword_t
is
std_logic_vector
(
63
downto
0
);
type
byte_array_t
is
array
(
natural
range
<>
)
of
byte_t
;
type
word_array_t
is
array
(
natural
range
<>
)
of
word_t
;
type
lword_array_t
is
array
(
natural
range
<>
)
of
lword_t
;
type
qword_array_t
is
array
(
natural
range
<>
)
of
qword_t
;
...
...
@@ -637,9 +636,7 @@ begin
procedure
read32_blt
(
addr
:
std_logic_vector
(
31
downto
0
);
am
:
vme_am_t
;
variable
data
:
out
lword_array_t
)
is
variable
res
:
lword_t
;
variable
data
:
out
lword_array_t
)
is
begin
VME_LWORD_n_i
<=
'0'
;
read_setup_addr
(
addr
,
am
);
...
...
@@ -664,9 +661,7 @@ begin
procedure
read16_blt
(
addr
:
std_logic_vector
(
31
downto
0
);
am
:
vme_am_t
;
variable
data
:
out
word_array_t
)
is
variable
res
:
lword_t
;
variable
data
:
out
word_array_t
)
is
begin
VME_LWORD_n_i
<=
'1'
;
read_setup_addr
(
addr
,
am
);
...
...
@@ -690,9 +685,7 @@ begin
procedure
read64_mblt
(
addr
:
std_logic_vector
(
31
downto
0
);
am
:
vme_am_t
;
variable
data
:
out
qword_array_t
)
is
variable
res
:
lword_t
;
variable
data
:
out
qword_array_t
)
is
begin
VME_LWORD_n_i
<=
'0'
;
read_setup_addr
(
addr
,
am
);
...
...
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