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VME64x core
Commits
19318a70
Commit
19318a70
authored
Oct 05, 2017
by
Tristan Gingold
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Plain Diff
Remove trailing spaces, fix max line length.
parent
4afd6871
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Showing
7 changed files
with
54 additions
and
53 deletions
+54
-53
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+1
-1
VME_CR_CSR_Space.vhd
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+2
-2
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+3
-3
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+1
-1
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+1
-1
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+4
-4
xvme64x_core_pkg.vhd
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+42
-41
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
19318a70
...
@@ -350,7 +350,7 @@ begin
...
@@ -350,7 +350,7 @@ begin
report
"bit set in AMCAP for not supported AM"
report
"bit set in AMCAP for not supported AM"
severity
failure
;
severity
failure
;
end
generate
;
end
generate
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Metastability
-- Metastability
------------------------------------------------------------------------------
------------------------------------------------------------------------------
...
...
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @
19318a70
...
@@ -196,7 +196,7 @@ architecture rtl of VME_CR_CSR_Space is
...
@@ -196,7 +196,7 @@ architecture rtl of VME_CR_CSR_Space is
constant
c_ADER_MASK
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000_00fd"
;
constant
c_ADER_MASK
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000_00fd"
;
-- Corresponding ADEM bits.
-- Corresponding ADEM bits.
constant
c_ADEM_MASK
:
std_logic_vector
(
31
downto
0
)
:
=
x"ffff_ff00"
;
constant
c_ADEM_MASK
:
std_logic_vector
(
31
downto
0
)
:
=
x"ffff_ff00"
;
-- CRAM
-- CRAM
type
t_cram
is
array
(
c_CRAM_SIZE
-1
downto
0
)
of
std_logic_vector
(
7
downto
0
);
type
t_cram
is
array
(
c_CRAM_SIZE
-1
downto
0
)
of
std_logic_vector
(
7
downto
0
);
...
@@ -366,7 +366,7 @@ begin
...
@@ -366,7 +366,7 @@ begin
-- behaviour to be compatible with the driver. The reset bit will
-- behaviour to be compatible with the driver. The reset bit will
-- be cleared at the next CSR write access.
-- be cleared at the next CSR write access.
s_reg_bit_reg
(
c_RESET_BIT
)
<=
'0'
;
s_reg_bit_reg
(
c_RESET_BIT
)
<=
'0'
;
csr_idx
:
=
s_addr
(
7
downto
4
);
csr_idx
:
=
s_addr
(
7
downto
4
);
csr_boff
:
=
s_addr
(
3
downto
2
);
csr_boff
:
=
s_addr
(
3
downto
2
);
case
csr_idx
is
case
csr_idx
is
...
...
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
19318a70
...
@@ -66,7 +66,7 @@ architecture rtl of VME_Funct_Match is
...
@@ -66,7 +66,7 @@ architecture rtl of VME_Funct_Match is
signal
s_function_sel
:
natural
range
0
to
7
;
signal
s_function_sel
:
natural
range
0
to
7
;
signal
s_function_sel_valid
:
std_logic
;
signal
s_function_sel_valid
:
std_logic
;
signal
s_decode_start_1
:
std_logic
;
signal
s_decode_start_1
:
std_logic
;
-- Selected function
-- Selected function
signal
s_function
:
std_logic_vector
(
7
downto
0
);
signal
s_function
:
std_logic_vector
(
7
downto
0
);
signal
s_ader_am_valid
:
std_logic_vector
(
7
downto
0
);
signal
s_ader_am_valid
:
std_logic_vector
(
7
downto
0
);
...
@@ -94,7 +94,7 @@ begin
...
@@ -94,7 +94,7 @@ begin
s_function_sel
<=
0
;
s_function_sel
<=
0
;
s_function_sel_valid
<=
'0'
;
s_function_sel_valid
<=
'0'
;
s_decode_start_1
<=
'0'
;
s_decode_start_1
<=
'0'
;
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
null
;
null
;
elsif
decode_start_i
=
'1'
then
elsif
decode_start_i
=
'1'
then
...
@@ -124,7 +124,7 @@ begin
...
@@ -124,7 +124,7 @@ begin
else
else
-- s_decode_start_1 is set.
-- s_decode_start_1 is set.
decode_done_o
<=
'1'
;
decode_done_o
<=
'1'
;
if
s_function_sel_valid
=
'1'
then
if
s_function_sel_valid
=
'1'
then
mask
:
=
(
others
=>
'0'
);
mask
:
=
(
others
=>
'0'
);
mask
(
c_ADEM_M
)
:
=
g_ADEM
(
s_function_sel
)(
c_ADEM_M
);
mask
(
c_ADEM_M
)
:
=
g_ADEM
(
s_function_sel
)(
c_ADEM_M
);
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
19318a70
...
@@ -483,7 +483,7 @@ begin
...
@@ -483,7 +483,7 @@ begin
s_dataPhase
<=
'0'
;
s_dataPhase
<=
'0'
;
end
if
;
end
if
;
if
s_DS_latch_count
=
0
then
if
s_DS_latch_count
=
0
or
s_transferType
=
MBLT
then
if
s_irq_sel
=
'1'
then
if
s_irq_sel
=
'1'
then
s_mainFSMstate
<=
DATA_TO_BUS
;
s_mainFSMstate
<=
DATA_TO_BUS
;
elsif
s_transferType
=
MBLT
and
s_MBLT_Data
=
'0'
then
elsif
s_transferType
=
MBLT
and
s_MBLT_Data
=
'0'
then
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
19318a70
...
@@ -142,7 +142,7 @@ package vme64x_pack is
...
@@ -142,7 +142,7 @@ package vme64x_pack is
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000ff00"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000ff00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
...
...
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
19318a70
...
@@ -37,10 +37,10 @@ use work.vme64x_pack.all;
...
@@ -37,10 +37,10 @@ use work.vme64x_pack.all;
entity
xvme64x_core
is
entity
xvme64x_core
is
generic
(
generic
(
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
-- CR/CSR
-- CR/CSR
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
...
...
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @
19318a70
...
@@ -78,47 +78,48 @@ package xvme64x_core_pkg is
...
@@ -78,47 +78,48 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------
------------------------------------------------------------------------------
component
xvme64x_core
component
xvme64x_core
generic
(
generic
(
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_SVEC_ID
;
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_SVEC_ID
;
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_REVISION_ID
;
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_REVISION_ID
;
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_ASCII_PTR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_ASCII_PTR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff33"
;
g_BEG_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff33"
;
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
);
port
(
port
(
clk_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
...
...
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