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VME64x core
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VME64x core
Commits
19318a70
Commit
19318a70
authored
Oct 05, 2017
by
Tristan Gingold
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Plain Diff
Remove trailing spaces, fix max line length.
parent
4afd6871
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7 changed files
with
54 additions
and
53 deletions
+54
-53
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+1
-1
VME_CR_CSR_Space.vhd
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+2
-2
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+3
-3
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+1
-1
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+1
-1
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+4
-4
xvme64x_core_pkg.vhd
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+42
-41
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
19318a70
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @
19318a70
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
19318a70
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
19318a70
...
...
@@ -483,7 +483,7 @@ begin
s_dataPhase
<=
'0'
;
end
if
;
if
s_DS_latch_count
=
0
then
if
s_DS_latch_count
=
0
or
s_transferType
=
MBLT
then
if
s_irq_sel
=
'1'
then
s_mainFSMstate
<=
DATA_TO_BUS
;
elsif
s_transferType
=
MBLT
and
s_MBLT_Data
=
'0'
then
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
19318a70
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
19318a70
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @
19318a70
...
...
@@ -95,6 +95,7 @@ package xvme64x_core_pkg is
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
...
...
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