Commit 20f51d45 authored by Tristan Gingold's avatar Tristan Gingold

Rename units (to follow file names).

parent af1eb06a
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: VME64xCore_Top (VME64xCore_Top.vhd) -- unit name: vme64x_core
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
-- --
-- The main blocks: -- The main blocks:
-- --
-- ______________________VME64xCore_Top_____________________ -- _______________________vme64x_core_______________________
-- | ________________ ________ ___________________ | -- | ________________ ________ ___________________ |
-- |___ | | | | | | | -- |___ | | | | | | |
-- | | | VME Bus | | Funct | | | | -- | | | VME Bus | | Funct | | | |
...@@ -51,8 +51,8 @@ ...@@ -51,8 +51,8 @@
-- delay that make impossible reproduce the WB PIPELINED protocol. -- delay that make impossible reproduce the WB PIPELINED protocol.
-- The WB Slave application must work with the same frequency as this vme64x -- The WB Slave application must work with the same frequency as this vme64x
-- core. -- core.
-- The main component of this core is the VME_bus on the left in the block -- The main component of this core is the VME_bus on the left in the block
-- diagram. Inside this component you can find the main finite state machine -- diagram. Inside this component you can find the main finite state machine
-- that coordinates all the synchronisms. -- that coordinates all the synchronisms.
-- The WB protocol is more faster than the VME protocol so to make independent -- The WB protocol is more faster than the VME protocol so to make independent
-- the two protocols a FIFO memory can be introduced. -- the two protocols a FIFO memory can be introduced.
...@@ -107,9 +107,9 @@ ...@@ -107,9 +107,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME64xCore_Top is entity vme64x_core is
generic ( generic (
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD; -- Clock period (ns) g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD; -- Clock period (ns)
g_WB_DATA_WIDTH : integer := c_DATA_WIDTH; -- WB data width: = 32 g_WB_DATA_WIDTH : integer := c_DATA_WIDTH; -- WB data width: = 32
...@@ -274,9 +274,9 @@ entity VME64xCore_Top is ...@@ -274,9 +274,9 @@ entity VME64xCore_Top is
-- lines. -- lines.
); );
end VME64xCore_Top; end vme64x_core;
architecture RTL of VME64xCore_Top is architecture rtl of vme64x_core is
signal s_reset : std_logic; signal s_reset : std_logic;
signal s_reset_n : std_logic; signal s_reset_n : std_logic;
...@@ -405,7 +405,7 @@ begin ...@@ -405,7 +405,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- VME Bus -- VME Bus
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
Inst_VME_bus : entity work.VME_bus inst_vme_bus : entity work.vme_bus
generic map ( generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD, g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH, g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
...@@ -480,7 +480,7 @@ begin ...@@ -480,7 +480,7 @@ begin
VME_BERR_o <= not s_vme_berr_n; -- The VME_BERR is asserted when '1' because VME_BERR_o <= not s_vme_berr_n; -- The VME_BERR is asserted when '1' because
-- the buffers on the board invert the logic. -- the buffers on the board invert the logic.
Inst_VME_Funct_Match : entity work.VME_Funct_Match inst_vme_funct_match : entity work.vme_funct_match
generic map ( generic map (
g_ADEM => c_ADEM, g_ADEM => c_ADEM,
g_AMCAP => c_AMCAP, g_AMCAP => c_AMCAP,
...@@ -508,7 +508,7 @@ begin ...@@ -508,7 +508,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Interrupter -- Interrupter
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
Inst_VME_IRQ_Controller : entity work.VME_IRQ_Controller inst_vme_irq_controller : entity work.vme_irq_controller
generic map ( generic map (
g_RETRY_TIMEOUT => 1000000 / g_CLOCK_PERIOD -- 1ms timeout g_RETRY_TIMEOUT => 1000000 / g_CLOCK_PERIOD -- 1ms timeout
) )
...@@ -525,7 +525,7 @@ begin ...@@ -525,7 +525,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CR/CSR space -- CR/CSR space
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : entity work.VME_CR_CSR_Space inst_vme_cr_csr_space : entity work.vme_cr_csr_space
generic map ( generic map (
g_MANUFACTURER_ID => g_MANUFACTURER_ID, g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID, g_BOARD_ID => g_BOARD_ID,
...@@ -574,7 +574,7 @@ begin ...@@ -574,7 +574,7 @@ begin
-- User CSR space -- User CSR space
gen_int_user_csr : if g_USER_CSR_EXT = false generate gen_int_user_csr : if g_USER_CSR_EXT = false generate
Inst_VME_User_CSR : entity work.VME_User_CSR inst_vme_user_csr : entity work.vme_user_csr
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => s_reset_n, rst_n_i => s_reset_n,
...@@ -596,4 +596,4 @@ begin ...@@ -596,4 +596,4 @@ begin
user_csr_data_o <= s_user_csr_data_o; user_csr_data_o <= s_user_csr_data_o;
user_csr_we_o <= s_user_csr_we; user_csr_we_o <= s_user_csr_we;
end RTL; end rtl;
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: vme64x_pack (vme64x_pack.vhd) -- unit name: vme64x_pkg
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -35,7 +35,7 @@ library ieee; ...@@ -35,7 +35,7 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
package vme64x_pack is package vme64x_pkg is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Constants -- Constants
...@@ -123,7 +123,7 @@ package vme64x_pack is ...@@ -123,7 +123,7 @@ package vme64x_pack is
-- Components -- Components
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component VME64xCore_Top component vme64x_core
generic ( generic (
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD; g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_WB_DATA_WIDTH : integer := c_DATA_WIDTH; g_WB_DATA_WIDTH : integer := c_DATA_WIDTH;
...@@ -220,4 +220,4 @@ package vme64x_pack is ...@@ -220,4 +220,4 @@ package vme64x_pack is
irq_i : in std_logic irq_i : in std_logic
); );
end component; end component;
end vme64x_pack; end vme64x_pkg;
...@@ -65,9 +65,9 @@ ...@@ -65,9 +65,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME_bus is entity vme_bus is
generic ( generic (
g_CLOCK_PERIOD : integer; g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer; g_WB_DATA_WIDTH : integer;
...@@ -135,9 +135,9 @@ entity VME_bus is ...@@ -135,9 +135,9 @@ entity VME_bus is
irq_pending_i : in std_logic; irq_pending_i : in std_logic;
irq_ack_o : out std_logic irq_ack_o : out std_logic
); );
end VME_bus; end vme_bus;
architecture RTL of VME_bus is architecture rtl of vme_bus is
-- Local data -- Local data
signal s_locDataIn : std_logic_vector(63 downto 0); signal s_locDataIn : std_logic_vector(63 downto 0);
signal s_locDataOut : std_logic_vector(63 downto 0); signal s_locDataOut : std_logic_vector(63 downto 0);
...@@ -769,4 +769,4 @@ begin ...@@ -769,4 +769,4 @@ begin
cr_csr_we_o <= '1' when s_conf_req = '1' and cr_csr_we_o <= '1' when s_conf_req = '1' and
s_WRITElatched_n = '0' s_WRITElatched_n = '0'
else '0'; else '0';
end RTL; end rtl;
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: VME_CR_CSR_Space (VME_CR_CSR_Space.vhd) -- unit name: vme_cr_csr_space
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -105,9 +105,9 @@ ...@@ -105,9 +105,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME_CR_CSR_Space is entity vme_cr_csr_space is
generic ( generic (
g_MANUFACTURER_ID : std_logic_vector(23 downto 0); g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0); g_BOARD_ID : std_logic_vector(31 downto 0);
...@@ -153,9 +153,9 @@ entity VME_CR_CSR_Space is ...@@ -153,9 +153,9 @@ entity VME_CR_CSR_Space is
ader_o : out t_ader_array(0 to 7) ader_o : out t_ader_array(0 to 7)
); );
end VME_CR_CSR_Space; end vme_cr_csr_space;
architecture rtl of VME_CR_CSR_Space is architecture rtl of vme_cr_csr_space is
signal s_addr : unsigned(18 downto 2); signal s_addr : unsigned(18 downto 2);
signal s_ga_parity : std_logic; signal s_ga_parity : std_logic;
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: VME_Funct_Match (VME_Funct_Match.vhd) -- unit name: vme_funct_match
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -34,9 +34,9 @@ ...@@ -34,9 +34,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME_Funct_Match is entity vme_funct_match is
generic ( generic (
g_ADEM : t_adem_array(0 to 7); g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7); g_AMCAP : t_amcap_array(0 to 7);
...@@ -60,9 +60,9 @@ entity VME_Funct_Match is ...@@ -60,9 +60,9 @@ entity VME_Funct_Match is
-- Set when sel_o is valid (decoding is done). -- Set when sel_o is valid (decoding is done).
decode_done_o : out std_logic decode_done_o : out std_logic
); );
end VME_Funct_Match; end vme_funct_match;
architecture rtl of VME_Funct_Match is architecture rtl of vme_funct_match is
-- Function index and ADEM from priority encoder -- Function index and ADEM from priority encoder
signal s_function_sel : natural range 0 to 7; signal s_function_sel : natural range 0 to 7;
signal s_function_sel_valid : std_logic; signal s_function_sel_valid : std_logic;
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: VME_IRQ_Controller (VME_IRQ_Controller.vhd) -- unit name: vme_irq_controller
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -125,9 +125,9 @@ ...@@ -125,9 +125,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME_IRQ_Controller is entity vme_irq_controller is
generic ( generic (
g_RETRY_TIMEOUT : integer range 1024 to 16777215 g_RETRY_TIMEOUT : integer range 1024 to 16777215
); );
...@@ -140,9 +140,9 @@ entity VME_IRQ_Controller is ...@@ -140,9 +140,9 @@ entity VME_IRQ_Controller is
irq_ack_i : in std_logic; irq_ack_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (7 downto 1) VME_IRQ_n_o : out std_logic_vector (7 downto 1)
); );
end VME_IRQ_Controller; end vme_irq_controller;
architecture Behavioral of VME_IRQ_Controller is architecture rtl of vme_irq_controller is
type t_retry_state is (WAIT_IRQ, WAIT_RETRY); type t_retry_state is (WAIT_IRQ, WAIT_RETRY);
...@@ -223,4 +223,4 @@ begin ...@@ -223,4 +223,4 @@ begin
end if; end if;
end if; end if;
end process; end process;
end Behavioral; end rtl;
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- http://www.ohwr.org/projects/vme64x-core -- http://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: VME_User_CSR (VME_User_CSR.vhd) -- unit name: vme_user_csr
-- --
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch> -- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch> -- Davide Pedretti <davide.pedretti@cern.ch>
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- reserved area of the defined CSR in previous versions of this core. -- reserved area of the defined CSR in previous versions of this core.
-- --
-- To achieve the previous memory map layout, it is necessary to set the -- To achieve the previous memory map layout, it is necessary to set the
-- following generics on the VME64xCore_Top: -- following generics on the vme64x_core:
-- --
-- g_BEG_USER_CSR => x"07ff33", -- g_BEG_USER_CSR => x"07ff33",
-- g_END_USER_CSR => x"07ff5f", -- g_END_USER_CSR => x"07ff5f",
...@@ -56,9 +56,9 @@ ...@@ -56,9 +56,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity VME_User_CSR is entity vme_user_csr is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
......
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
entity xvme64x_core is entity xvme64x_core is
generic ( generic (
...@@ -155,7 +155,7 @@ architecture wrapper of xvme64x_core is ...@@ -155,7 +155,7 @@ architecture wrapper of xvme64x_core is
begin -- wrapper begin -- wrapper
U_Wrapped_VME : VME64xCore_Top U_Wrapped_VME : vme64x_core
generic map ( generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD, g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH, g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
......
...@@ -34,11 +34,11 @@ entity top_tb is ...@@ -34,11 +34,11 @@ entity top_tb is
end; end;
library ieee; library ieee;
use std.textio.all;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_textio.all; use ieee.std_logic_textio.all;
use work.vme64x_pack.all; use work.vme64x_pkg.all;
use std.textio.all;
architecture behaviour of top_tb is architecture behaviour of top_tb is
subtype cfg_addr_t is std_logic_vector (19 downto 0); subtype cfg_addr_t is std_logic_vector (19 downto 0);
...@@ -263,7 +263,7 @@ begin ...@@ -263,7 +263,7 @@ begin
xor slave_ga (1) xor slave_ga (0)); xor slave_ga (1) xor slave_ga (0));
end block; end block;
vme64xcore: entity work.VME64xCore_Top vme64xcore: entity work.vme64x_core
generic map (g_CLOCK_PERIOD => g_CLOCK_PERIOD, generic map (g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH, g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH, g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
......
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