Move VME64xCore_Top prototype to vme64x_pack.vhd

The component prototype for VME64xCore_Top has been moved from xvme64x_core.vhd to vme64x_pack.vhd so that it is with the other prototypes. Signed-off-by: Tom Levens <tom.levens@cern.ch>

Move VME64xCore_Top prototype to vme64x_pack.vhd
The component prototype for VME64xCore_Top has been moved from xvme64x_core.vhd to vme64x_pack.vhd so that it is with the other prototypes. Signed-off-by: Tom Levens <tom.levens@cern.ch>
29269caa · Tom Levens · 6994f35b · 29269caa · 29269caa
Commit 29269caa authored Jan 10, 2017 by Tom Levens
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vme64x_pack.vhd hdl/vme64x-core/rtl/vme64x_pack.vhd +53 -0

xvme64x_core.vhd hdl/vme64x-core/rtl/xvme64x_core.vhd +0 -52

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--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -476,6 +476,59 @@ package vme64x_pack is
  -- Components
  ------------------------------------------------------------------------------

+  component VME64xCore_Top
+    generic (
+      g_wb_data_width : integer := 32;
+      g_wb_addr_width : integer := 64;
+      g_CRAM_SIZE     : integer := 1024;
+      g_adem_a24      : std_logic_vector(31 downto 0);
+      g_adem_a32      : std_logic_vector(31 downto 0);
+      g_clock         : integer
+    );
+    port (
+      clk_i           : in  std_logic;
+      rst_n_i         : in  std_logic;
+      VME_AS_n_i      : in  std_logic;
+      VME_RST_n_i     : in  std_logic;
+      VME_WRITE_n_i   : in  std_logic;
+      VME_AM_i        : in  std_logic_vector(5 downto 0);
+      VME_DS_n_i      : in  std_logic_vector(1 downto 0);
+      VME_GA_i        : in  std_logic_vector(5 downto 0);
+      VME_BERR_o      : out std_logic;
+      VME_DTACK_n_o   : out std_logic;
+      VME_RETRY_n_o   : out std_logic;
+      VME_LWORD_n_i   : in  std_logic;
+      VME_LWORD_n_o   : out std_logic;
+      VME_ADDR_i      : in  std_logic_vector(31 downto 1);
+      VME_ADDR_o      : out std_logic_vector(31 downto 1);
+      VME_DATA_i      : in  std_logic_vector(31 downto 0);
+      VME_DATA_o      : out std_logic_vector(31 downto 0);
+      VME_IRQ_o       : out std_logic_vector(6 downto 0);
+      VME_IACKIN_n_i  : in  std_logic;
+      VME_IACK_n_i    : in  std_logic;
+      VME_IACKOUT_n_o : out std_logic;
+      VME_DTACK_OE_o  : out std_logic;
+      VME_DATA_DIR_o  : out std_logic;
+      VME_DATA_OE_N_o : out std_logic;
+      VME_ADDR_DIR_o  : out std_logic;
+      VME_ADDR_OE_N_o : out std_logic;
+      VME_RETRY_OE_o  : out std_logic;
+      DAT_i           : in  std_logic_vector(g_wb_data_width-1 downto 0);
+      DAT_o           : out std_logic_vector(g_wb_data_width-1 downto 0);
+      ADR_o           : out std_logic_vector(g_wb_addr_width-1 downto 0);
+      CYC_o           : out std_logic;
+      ERR_i           : in  std_logic;
+      RTY_i           : in  std_logic;
+      SEL_o           : out std_logic_vector(g_wb_data_width/8-1 downto 0);
+      STB_o           : out std_logic;
+      ACK_i           : in  std_logic;
+      WE_o            : out std_logic;
+      STALL_i         : in  std_logic;
+      INT_ack_o       : out std_logic;
+      IRQ_i           : in  std_logic
+    );
+  end component;
+
  component VME_bus is
    generic (
      g_clock         : integer := c_clk_period;

--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd
@@ -82,58 +82,6 @@ end xvme64x_core;

 architecture wrapper of xvme64x_core is

-  component VME64xCore_Top
-    generic (
-      g_wb_data_width : integer := 32;
-      g_wb_addr_width : integer := 64;
-      g_CRAM_SIZE     : integer := 1024;
-      g_adem_a24      : std_logic_vector(31 downto 0);
-      g_adem_a32      : std_logic_vector(31 downto 0);
-      g_clock : integer
-    );
-    port (
-      clk_i           : in  std_logic;
-      rst_n_i         : in  std_logic;
-      VME_AS_n_i      : in  std_logic;
-      VME_RST_n_i     : in  std_logic;
-      VME_WRITE_n_i   : in  std_logic;
-      VME_AM_i        : in  std_logic_vector(5 downto 0);
-      VME_DS_n_i      : in  std_logic_vector(1 downto 0);
-      VME_GA_i        : in  std_logic_vector(5 downto 0);
-      VME_BERR_o      : out std_logic;
-      VME_DTACK_n_o   : out std_logic;
-      VME_RETRY_n_o   : out std_logic;
-      VME_LWORD_n_i   : in  std_logic;
-      VME_LWORD_n_o   : out std_logic;
-      VME_ADDR_i      : in  std_logic_vector(31 downto 1);
-      VME_ADDR_o      : out std_logic_vector(31 downto 1);
-      VME_DATA_i      : in  std_logic_vector(31 downto 0);
-      VME_DATA_o      : out std_logic_vector(31 downto 0);
-      VME_IRQ_o       : out std_logic_vector(6 downto 0);
-      VME_IACKIN_n_i  : in  std_logic;
-      VME_IACK_n_i    : in  std_logic;
-      VME_IACKOUT_n_o : out std_logic;
-      VME_DTACK_OE_o  : out std_logic;
-      VME_DATA_DIR_o  : out std_logic;
-      VME_DATA_OE_N_o : out std_logic;
-      VME_ADDR_DIR_o  : out std_logic;
-      VME_ADDR_OE_N_o : out std_logic;
-      VME_RETRY_OE_o  : out std_logic;
-      DAT_i           : in  std_logic_vector(g_wb_data_width-1 downto 0);
-      DAT_o           : out std_logic_vector(g_wb_data_width-1 downto 0);
-      ADR_o           : out std_logic_vector(g_wb_addr_width-1 downto 0);
-      CYC_o           : out std_logic;
-      ERR_i           : in  std_logic;
-      RTY_i           : in  std_logic;
-      SEL_o           : out std_logic_vector(g_wb_data_width/8-1 downto 0);
-      STB_o           : out std_logic;
-      ACK_i           : in  std_logic;
-      WE_o            : out std_logic;
-      STALL_i         : in  std_logic;
-      INT_ack_o       : out std_logic;
-      IRQ_i           : in  std_logic);
-  end component;
-
  signal dat_out, dat_in : std_logic_vector(31 downto 0);
  signal adr_out         : std_logic_vector(63 downto 0);