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VME64x core
Commits
3ed18b06
Commit
3ed18b06
authored
Nov 27, 2017
by
Tristan Gingold
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vme_bus: add c_ prefix to num_latchDS.
parent
6067d993
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4 deletions
+4
-4
GD-vme64x-core-review.txt
doc/review-2017-11-13/GD-vme64x-core-review.txt
+1
-1
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+3
-3
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doc/review-2017-11-13/GD-vme64x-core-review.txt
View file @
3ed18b06
...
...
@@ -63,7 +63,7 @@
- why reset is active high (rst_i) and not active low like in all other modules?
Done.
- constant num_latchDS misses "c_" prefix
OK
.
Done
.
- line 431: 3 nested if-s. How about simplifying to:
if decode_done_i = '1' and decode_sel_i = '1' and module_enable_i = '1'then
(...)
...
...
hdl/rtl/vme_bus.vhd
View file @
3ed18b06
...
...
@@ -234,7 +234,7 @@ architecture rtl of vme_bus is
-- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
-- (max skew for the slave is 20 ns)
constant
num_latchDS
:
natural
range
1
to
8
:
=
constant
c_num_latchDS
:
natural
range
1
to
8
:
=
(
20
+
g_CLOCK_PERIOD
-
1
)
/
g_CLOCK_PERIOD
;
signal
s_DS_latch_count
:
unsigned
(
2
downto
0
);
...
...
@@ -389,7 +389,7 @@ begin
s_irq_sel
<=
'0'
;
-- DS latch counter
s_DS_latch_count
<=
to_unsigned
(
num_latchDS
,
3
);
s_DS_latch_count
<=
to_unsigned
(
c_
num_latchDS
,
3
);
-- VITA-1 Rule 2.6
-- A Slave MUST NOT respond with a falling edge on DTACK* during
...
...
@@ -656,7 +656,7 @@ begin
VME_DTACK_n_o
<=
'1'
;
-- DS latch counter
s_DS_latch_count
<=
to_unsigned
(
num_latchDS
,
3
);
s_DS_latch_count
<=
to_unsigned
(
c_
num_latchDS
,
3
);
if
s_irq_sel
=
'1'
then
s_mainFSMstate
<=
WAIT_END
;
...
...
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