Commit 45cb91f4 authored by Tom Levens's avatar Tom Levens

Fix references to ANSI/VITA standards

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 44f9345f
......@@ -324,7 +324,7 @@ begin
s_AMlatched <= vme_am_i;
if vme_iack_n_i = '1' then
-- VITA-1 Rule 2.11
-- ANSI/VITA 1-1994 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS;
else
......@@ -356,7 +356,7 @@ begin
-- DS latch counter
s_DS_latch_count <= to_unsigned (c_num_latchDS, 3);
-- VITA-1 Rule 2.6
-- ANSI/VITA 1-1994 Rule 2.6
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
-- capability.
......@@ -414,7 +414,7 @@ begin
-- Note: before entering this state, s_DS_latch_count must be set.
if vme_ds_n_i /= "11" then
-- VITAL-1 Table 4-1
-- ANSI/VITA 1-1994 Table 4-1
-- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
......@@ -429,7 +429,7 @@ begin
-- This state is necessary indeed the VME master can assert the
-- DS lines not at the same time.
-- VITA-1 Rule 2.53a
-- ANSI/VITA 1-1994 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT
-- drive the D[] lines until DSA* goes low.
vme_data_dir_o <= s_WRITElatched_n;
......@@ -501,7 +501,7 @@ begin
end case;
end if;
-- VITA-1 Rule 2.6
-- ANSI/VITA 1-1994 Rule 2.6
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
-- capability.
......@@ -604,7 +604,7 @@ begin
vme_lword_n_o <= s_locDataOut(32);
vme_data_o <= s_locDataOut(31 downto 0);
-- VITA-1 Rule 2.54a
-- ANSI/VITA 1-1994 Rule 2.54a
-- During all read cycles, the responding Slave MUST NOT drive
-- DTACK* low before it drives D[].
s_mainFSMstate <= DTACK_LOW;
......@@ -621,7 +621,7 @@ begin
vme_dtack_n_o <= '0';
end if;
-- VITA-1 Rule 2.57
-- ANSI/VITA 1-1994 Rule 2.57
-- Once the responding Slave has driven DTACK* or BERR* low, it
-- MUST NOT release them or drive DTACK* high until it detects
-- both DS0* and DS1* high.
......
......@@ -316,8 +316,8 @@ begin
-- Write
process (clk_i)
-- Write to ADER bytes, if implemented. Take advantage of VITAL-1-1 Rule
-- 10.19
-- Write to ADER bytes, if implemented. Take advantage of
-- ANSI/VITA 1.1-1997 Rule 10.19
procedure Set_ADER (idx : natural range 0 to 7) is
variable v_byte : integer;
begin
......@@ -360,7 +360,7 @@ begin
s_reg_bit_reg <= s_reg_bit_reg or data_i;
when "01" => -- Bit Clr
s_reg_bit_reg <= s_reg_bit_reg and not data_i;
-- VITAL-1-1 Rule 10.27
-- ANSI/VITA 1.1-1997 Rule 10.27
-- 4) Ownership shall be released by writing any value with
-- bit 2 set (eg 0x04) to the CSR Bit Clear Register
-- located at 0x7fff7. This clears the CRAM_OWNER
......@@ -370,7 +370,7 @@ begin
s_reg_cram_owner <= x"00";
end if;
when "00" => -- CRAM_OWNER
-- VITAL-1-1 Rule 10.27
-- ANSI/VITA 1.1-1997 Rule 10.27
-- 2) Writing to CRAM_OWNER register when it contains a non-
-- zero value shall not change the value of the
-- CRAM_OWNER. That allows the first master that writes
......@@ -457,7 +457,7 @@ begin
if rst_n_i = '0' then
s_csr_data <= x"00";
else
-- VITAL-1-1 Rule 10.14
-- ANSI/VITA 1.1-1997 Rule 10.14
-- All unimplemented locations in the Defined CSR Area shall read as
-- 0x00
s_csr_data <= x"00";
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment