xvme64x_core: add g_WB_MODE generic to select between classic/pipelined.

4d39f9df · Tristan Gingold · 1204aeca · 4d39f9df · 4d39f9df · 4d39f9df
Commit 4d39f9df authored Jul 24, 2019 by Tristan Gingold
Hide whitespace changes
Inline Side-by-side

Showing with 22 additions and 4 deletions

vme64x_core.vhd hdl/rtl/vme64x_core.vhd +1 -0

vme_bus.vhd hdl/rtl/vme_bus.vhd +16 -2

xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +5 -2

No files found.
--- a/hdl/rtl/vme64x_core.vhd
+++ b/hdl/rtl/vme64x_core.vhd
@@ -114,6 +114,7 @@ begin
      g_ENABLE_CR_CSR    => g_ENABLE_CR_CSR,
      g_USER_CSR_EXT     => g_USER_CSR_EXT,
      g_WB_GRANULARITY   => g_WB_GRANULARITY,
+      g_WB_MODE          => CLASSIC,
      g_MANUFACTURER_ID  => g_MANUFACTURER_ID,
      g_BOARD_ID         => g_BOARD_ID,
      g_REVISION_ID      => g_REVISION_ID,

--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -34,7 +34,8 @@ use work.wishbone_pkg.all;
 entity vme_bus is
  generic (
    g_CLOCK_PERIOD  : integer;
-    g_WB_GRANULARITY  : t_wishbone_address_granularity
+    g_WB_GRANULARITY  : t_wishbone_address_granularity;
+    g_WB_MODE         : t_wishbone_interface_mode
  );
  port (
    clk_i           : in  std_logic;
@@ -199,6 +200,9 @@ architecture rtl of vme_bus is

  signal s_err                      : std_logic;

+  -- Stall status.  Set to one until wb_stall_i is cleared.
+  signal s_stall                    : std_logic;
+
  -- Calculate the number of LATCH DS states necessary to match the timing
  -- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
  -- (max skew for the slave is 20 ns)
@@ -515,6 +519,7 @@ begin
              -- Start WB cycle.
              wb_cyc_o <= s_card_sel;
              wb_stb_o <= s_card_sel;
+              s_stall  <= '1';  -- Can stall
              s_err <= '0';
            end if;

@@ -526,7 +531,15 @@ begin
            vme_addr_dir_o   <= s_vme_addr_dir;

            -- Assert STB if stall was asserted.
-            wb_stb_o <= s_card_sel and wb_stall_i;
+            case g_WB_MODE is
+              when CLASSIC =>
+                -- Maintain STB.
+                wb_stb_o <= s_card_sel;
+              when PIPELINED =>
+                -- Maintain STB if stall was set in the previous cycle.
+                wb_stb_o <= s_card_sel and s_stall and wb_stall_i;
+            end case;
+            s_stall  <= s_stall and wb_stall_i;

            if s_conf_sel = '1'
              or (s_card_sel = '1' and (wb_ack_i = '1' or wb_err_i = '1'))
@@ -590,6 +603,7 @@ begin

            if wb_ack_i = '0' then
              wb_stb_o <= '1';
+              s_stall  <= '1';
              s_mainFSMstate <= MEMORY_REQ;
            else
              s_mainFSMstate <= MEMORY_PAUSE;

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -63,6 +63,9 @@ entity xvme64x_core is
    --       WB address bits 1:0 are always 0.
    g_WB_GRANULARITY  : t_wishbone_address_granularity;

+    -- Wishbone mode: classic or pipeline.
+    g_WB_MODE         : t_wishbone_interface_mode := CLASSIC;
+
    -- Manufacturer ID: IEEE OUID
    --                  e.g. CERN is 0x080030
    g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
@@ -184,7 +187,6 @@ architecture rtl of xvme64x_core is

  signal s_reset_n              : std_logic;

-  signal s_vme_irq_n_o          : std_logic_vector( 7 downto 1);
  signal s_irq_ack              : std_logic;
  signal s_irq_pending          : std_logic;
  signal s_ga                   : std_logic_vector( 4 downto 0);
@@ -310,7 +312,8 @@ begin
  inst_vme_bus : entity work.vme_bus
    generic map (
      g_CLOCK_PERIOD   => g_CLOCK_PERIOD,
-      g_WB_GRANULARITY => g_WB_GRANULARITY)
+      g_WB_GRANULARITY => g_WB_GRANULARITY,
+      g_WB_MODE        => g_WB_MODE)
    port map (
      clk_i           => clk_i,
      rst_n_i         => s_reset_n,