Use a separate pin for the interrupt input line.

58d3d619 · Tristan Gingold · 5bd45fd2 · 58d3d619 · 58d3d619 · 58d3d619
Commit 58d3d619 authored Mar 06, 2018 by Tristan Gingold
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Showing with 10 additions and 2 deletions

vme64x_core.vhd hdl/rtl/vme64x_core.vhd +2 -0

xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +6 -1

top_tb.vhd hdl/testbench/simple_tb/top_tb.vhd +2 -1

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--- a/hdl/rtl/vme64x_core.vhd
+++ b/hdl/rtl/vme64x_core.vhd
@@ -93,6 +93,7 @@ entity vme64x_core is
    wb_sel_o        : out t_wishbone_byte_select;
    wb_we_o         : out std_logic;
    wb_dat_o        : out t_wishbone_data;
+    int_i           : std_logic;
    irq_ack_o       : out std_logic;
    irq_level_i     : std_logic_vector(2 downto 0);
    irq_vector_i    : std_logic_vector(7 downto 0);
@@ -190,6 +191,7 @@ begin
      wb_o.sel        => wb_sel_o,
      wb_o.we         => wb_we_o,
      wb_o.dat        => wb_dat_o,
+      int_i           => int_i,
      irq_ack_o       => irq_ack_o,
      irq_level_i     => irq_level_i,
      irq_vector_i    => irq_vector_i,

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -111,6 +111,11 @@ entity xvme64x_core is
    wb_i            : in  t_wishbone_master_in;
    wb_o            : out t_wishbone_master_out;
+    -- Interrupt input from the master side.
+    -- Previously it was part of the wishbone interface, but is now separate
+    -- as interrupt is not defined by wishbone.
+    int_i           : in std_logic;
    -- When the IRQ controller acknowledges the Interrupt cycle it sends a
    -- pulse to the IRQ Generator.
    irq_ack_o       : out std_logic;
@@ -376,7 +381,7 @@ begin
      clk_i           => clk_i,
      rst_n_i         => s_reset_n,
      INT_Level_i     => s_irq_level,
-      INT_Req_i       => wb_i.int,
+      INT_Req_i       => int_i,
      irq_pending_o   => s_irq_pending,
      irq_ack_i       => s_irq_ack,
      VME_IRQ_n_o     => vme_o.irq_n

--- a/hdl/testbench/simple_tb/top_tb.vhd
+++ b/hdl/testbench/simple_tb/top_tb.vhd
@@ -347,7 +347,8 @@ begin
        wb_WE_o         => WE_o,
        wb_STALL_i      => STALL_i,
        wb_rty_i        => rty_i,
-        wb_int_i        => irq_i,
+        wb_int_i        => '0',
+        int_i           => irq_i,
        irq_level_i     => irq_level_i,
        irq_vector_i    => irq_vector_i,
        user_csr_addr_o => user_csr_addr_o,