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VME64x core
Commit 6a0cbb71 authored by mcattin's avatar mcattin
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Dir. restruct. 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@132 665b4545-5c6b-4c24-801b-41150b02b44b
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README.txt
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......@@ -13,23 +13,25 @@ Matthieu Cattin
| |-- specifications
| `-- user_guides
|-- hdl
| |-- boards
| | |-- svec
| | | |-- ip_cores
| | | |-- rtl
| | | |-- sim
| | | `-- syn
| | `-- vfc
| | |-- ip_cores
| | |-- rtl
| | |-- sim
| | `-- syn
| `-- vme64x-core
| |-- ip_cores
| |-- rtl
| |-- sim
| `-- wb_gen
`-- sw
`-- vfc
`-- python
| |-- boards -> Board specific stuff
| | |-- svec -> Board's directory, put the .ucf here
| | | |-- ip_cores -> Board specific generated IP cores (e.g. FIFO, RAM, etc...)
| | | |-- rtl -> Board specific RTL HDL sources (top level, specific blocks, etc..)
| | | |-- sim -> Board level simulation (testbenches, simulation scripts, etc...)
| | | |-- syn -> Synthesis directory (ISE project, chipscope files)
| | | `-- wb_gen -> Wishbone generator source files
| | `-- vfc -> Board specific stuff
| | |-- ip_cores -> Board's directory, put the .ucf here
| | |-- rtl -> Board specific RTL HDL sources (top level, specific blocks, etc..)
| | |-- sim -> Board level simulation (testbenches, simulation scripts, etc...)
| | |-- syn -> Synthesis directory (ISE project, chipscope files)
| | `-- wb_gen -> Wishbone generator source files
| `-- vme64x-core -> Core's dircetory
| |-- ip_cores -> Core generated IP cores (e.g. FIFO, RAM, etc...)
| |-- rtl -> Core RTL HDL sources (core top level, core sub-blocks, packages, etc...)
| |-- sim -> Core simulation (testbenches, simulation scripts, etc...)
| `-- wb_gen -> Wishbone generator source files
`-- sw -> Software directory
`-- vfc -> Board specific software
`-- python -> Python programs
makedir/Makefile deleted 100644 → 0
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makedir/Makefile.bkp deleted 100644 → 0
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########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
WORK_NAME := work
MODELSIM_INI_PATH := /etc/modelsim/modeltech
VCOM_FLAGS := -nologo -quiet -93 -modelsimini ./modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -nologo -quiet -sv -modelsimini $(PWD)/modelsim.ini
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../HDL/VME64e_ActHDL_src/VME_pack.vhd \
../HDL/VME64e_ActHDL_src/VME_CSR_pack.vhd \
../HDL/NOIP_cores/fifo/common_components.vhd \
../HDL/VME64e_ActHDL_src/VME_CR_pack.vhd \
../HDL/VME64e_ActHDL_src/VME_bus.vhd \
../HDL/VME64e_ActHDL_src/SharedComps.vhd \
../HDL/NOIP_cores/DpRam/DpBlockRam.vhd \
../HDL/NOIP_cores/DpRam/TrueDpBlockRam.vhd \
../HDL/VME64e_ActHDL_src/wb_dma.vhd \
../HDL/VFC_dev/VME64xCore_NoIpTop.vhd \
VHDL_OBJ := work/VME_pack/.VME_pack_vhd \
work/VME_CSR_pack/.VME_CSR_pack_vhd \
work/common_components/.common_components_vhd \
work/VME_CR_pack/.VME_CR_pack_vhd \
work/VME_bus/.VME_bus_vhd \
work/SharedComps/.SharedComps_vhd \
work/DpBlockRam/.DpBlockRam_vhd \
work/TrueDpBlockRam/.TrueDpBlockRam_vhd \
work/wb_dma/.wb_dma_vhd \
work/VME64xCore_NoIpTop/.VME64xCore_NoIpTop_vhd \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< .
clean:
rm -rf ./modelsim.ini $(LIBS) $(WORK_NAME)
.PHONY: clean
wave: sim
do wave.do
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/VME_pack/.VME_pack_vhd: ../HDL/VME64e_ActHDL_src/VME_pack.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/VME_pack.vhd && mkdir -p work/VME_pack && touch work/VME_pack/.VME_pack_vhd
work/VME_CSR_pack/.VME_CSR_pack_vhd: ../HDL/VME64e_ActHDL_src/VME_CSR_pack.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/VME_CSR_pack.vhd && mkdir -p work/VME_CSR_pack && touch work/VME_CSR_pack/.VME_CSR_pack_vhd
work/VME_CSR_pack/.VME_CSR_pack: \
work/VME_pack/.VME_pack
work/common_components/.common_components_vhd: ../HDL/NOIP_cores/fifo/common_components.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/NOIP_cores/fifo/common_components.vhd && mkdir -p work/common_components && touch work/common_components/.common_components_vhd
work/VME_CR_pack/.VME_CR_pack_vhd: ../HDL/VME64e_ActHDL_src/VME_CR_pack.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/VME_CR_pack.vhd && mkdir -p work/VME_CR_pack && touch work/VME_CR_pack/.VME_CR_pack_vhd
work/VME_CR_pack/.VME_CR_pack: \
work/VME_pack/.VME_pack
work/VME_bus/.VME_bus_vhd: ../HDL/VME64e_ActHDL_src/VME_bus.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/VME_bus.vhd && mkdir -p work/VME_bus && touch work/VME_bus/.VME_bus_vhd
work/VME_bus/.VME_bus: \
work/VME_CR_pack/.VME_CR_pack \
work/VME_CSR_pack/.VME_CSR_pack \
work/VME_pack/.VME_pack
work/SharedComps/.SharedComps_vhd: ../HDL/VME64e_ActHDL_src/SharedComps.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/SharedComps.vhd && mkdir -p work/SharedComps && touch work/SharedComps/.SharedComps_vhd
work/DpBlockRam/.DpBlockRam_vhd: ../HDL/NOIP_cores/DpRam/DpBlockRam.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/NOIP_cores/DpRam/DpBlockRam.vhd && mkdir -p work/DpBlockRam && touch work/DpBlockRam/.DpBlockRam_vhd
work/TrueDpBlockRam/.TrueDpBlockRam_vhd: ../HDL/NOIP_cores/DpRam/TrueDpBlockRam.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/NOIP_cores/DpRam/TrueDpBlockRam.vhd && mkdir -p work/TrueDpBlockRam && touch work/TrueDpBlockRam/.TrueDpBlockRam_vhd
work/wb_dma/.wb_dma_vhd: ../HDL/VME64e_ActHDL_src/wb_dma.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VME64e_ActHDL_src/wb_dma.vhd && mkdir -p work/wb_dma && touch work/wb_dma/.wb_dma_vhd
work/wb_dma/.wb_dma: \
work/common_components/.common_components
work/VME64xCore_NoIpTop/.VME64xCore_NoIpTop_vhd: ../HDL/VFC_dev/VME64xCore_NoIpTop.vhd
vcom $(VCOM_FLAGS) -work work ../HDL/VFC_dev/VME64xCore_NoIpTop.vhd && mkdir -p work/VME64xCore_NoIpTop && touch work/VME64xCore_NoIpTop/.VME64xCore_NoIpTop_vhd
work/VME64xCore_NoIpTop/.VME64xCore_NoIpTop: \
work/VME_CR_pack/.VME_CR_pack \
work/common_components/.common_components
makedir/Manifest.py deleted 100644 → 0
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target = "xilinx"
action = "simulation"
modules = {"local" : ["../../../simlibs/unisim/","../HDL", "../HDL/verilog_tb"]}
makedir/modelsim.ini deleted 100755 → 0
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