Commit 6d88bf97 authored by Tom Levens's avatar Tom Levens

Add generics to configure CR space

Generics have been added to configure all values (ADEM, AMCAP, XAMCAP,
DAWPR, etc) in the CR space. This implements Feature #767 and #791 and
invalidates Bug #1403.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 7a8f2b5c
......@@ -6,8 +6,6 @@ files = [ "xvme64x_core.vhd",
"VME_Am_Match.vhd",
"VME_bus.vhd",
"VME_CR_CSR_Space.vhd",
"VME_CR_pack.vhd",
"VME_CSR_pack.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_Init.vhd",
......
......@@ -108,7 +108,6 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
entity VME64xCore_Top is
generic (
......@@ -116,22 +115,16 @@ entity VME64xCore_Top is
g_wb_data_width : integer := c_width; -- WB data width: must be 32 or 64
g_wb_addr_width : integer := c_addr_width; -- WB address width: 64 or less
---------------------------------------------------------------------------
-- CR/CSR
---------------------------------------------------------------------------
-- CRAM
g_CRAM_Size : integer := c_CRAM_SIZE;
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_ManufacturerID : integer := c_CERN_ID;
g_manufacturer_id : std_logic_vector(23 downto 0) := x"000000";
-- Board ID: Per manufacturer, each board shall have an unique ID
-- e.g. SVEC = 408 (CERN IDs: http://cern.ch/boardid)
g_BoardID : integer := c_SVEC_ID;
g_board_id : std_logic_vector(31 downto 0) := x"00000000";
-- Revision ID: user defined revision code
g_RevisionID : integer := c_RevisionID;
g_revision_id : std_logic_vector(31 downto 0) := x"00000000";
-- Program ID: Defined per AV1:
-- 0x00 = Not used
......@@ -141,12 +134,71 @@ entity VME64xCore_Top is
-- 0x80-0xEF = Reserved for future use
-- 0xF0-0xFE = Reserved for Boot Firmware (P1275)
-- 0xFF = Not to be used
g_ProgramID : integer := 90;
-- The default values can be found in the vme64x_pack;
g_adem_a24 : std_logic_vector(31 downto 0) := x"ff800000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_program_id : std_logic_vector(7 downto 0) := x"00";
-- Pointer to a user defined ASCII string
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
-- User CR/CSR, CRAM & serial number pointers
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
-- Function 0
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 1
g_f1_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 2
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 3
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 4
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 5
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 6
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 7
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -213,23 +265,8 @@ end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
impure function f_setup_window_sizes(cr : t_cr_array) return t_cr_array is
variable tmp : t_cr_array(2**12 downto 0);
begin
tmp := cr;
tmp(16#188#) := g_adem_a32(31 downto 24);
tmp(16#189#) := g_adem_a32(23 downto 16);
tmp(16#18A#) := g_adem_a32(15 downto 8);
tmp(16#18B#) := g_adem_a32(7 downto 0);
tmp(16#18c#) := g_adem_a24(31 downto 24);
tmp(16#18d#) := g_adem_a24(23 downto 16);
tmp(16#18e#) := g_adem_a24(15 downto 8);
tmp(16#18f#) := g_adem_a24(7 downto 0);
return tmp;
end function;
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(11 downto 0);
......@@ -308,7 +345,7 @@ begin
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size
g_cram_size => f_size(g_beg_cram, g_end_cram)
)
port map (
clk_i => clk_i,
......@@ -436,13 +473,24 @@ begin
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_cram_size => g_cram_size,
g_cram_size => f_size(g_beg_cram, g_end_cram),
g_wb_data_width => g_wb_data_width,
g_CRspace => f_setup_window_sizes(c_cr_array),
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
g_cr_space => f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
g_beg_cram, g_end_cram,
g_beg_user_csr, g_end_user_csr,
g_beg_sn, g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr
)
)
port map (
clk_i => clk_i,
......
......@@ -39,7 +39,7 @@ use work.vme64x_pack.all;
entity VME_CRAM is
generic (
dl : integer;
al : integer := f_log2_size(c_CRAM_SIZE)
al : integer
);
port (
clk : in std_logic;
......
......@@ -136,18 +136,12 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
entity VME_CR_CSR_Space is
generic (
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array := c_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
g_cram_size : integer;
g_wb_data_width : integer;
g_cr_space : t_cr_array
);
port (
-- VMEbus.vhd signals
......@@ -189,11 +183,10 @@ end VME_CR_CSR_Space;
architecture Behavioral of VME_CR_CSR_Space is
signal s_CSRarray : t_CSRarray; -- Array of CSR registers
signal s_CSRarray : t_csr_array; -- Array of CSR registers
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CR_Space : t_cr_array(2**12 downto 0);
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
......@@ -213,13 +206,11 @@ begin
-- out error in the VME bus.
--s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
-- CR
process(clk_i)
begin
if rising_edge(clk_i) then
CR_data <= s_CR_Space(to_integer(unsigned(CR_addr)));
CR_data <= g_cr_space(to_integer(unsigned(CR_addr)));
end if;
end process;
......@@ -236,8 +227,8 @@ begin
if reset = '1' then
s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0';
for i in 254 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i);
for i in BAR-1 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= x"00";
end loop;
elsif s_bar_written = '0' and s_odd_parity = '1' then
-- initialization of BAR reg to access the CR/CSR space
......
This diff is collapsed.
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CSR_pack (VME_CSR_pack.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: This file defines the default configuration of the CSR space
-- after power-up or software reset.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray := (
BAR => x"00", -- CR/CSR BAR
BIT_SET_CLR_REG => x"00", -- Bit set register
-- 0x10 = module enable
USR_BIT_SET_CLR_REG => x"00", -- Bit clear register
CRAM_OWNER => x"00", -- CRAM_OWNER
FUNC0_ADER_0 => x"00", -- A32_S "24"
FUNC0_ADER_1 => x"00", -- "00"
FUNC0_ADER_2 => x"00", -- "00"
FUNC0_ADER_3 => x"00", -- "c0"
FUNC1_ADER_0 => x"00", -- A24_S "e4"
FUNC1_ADER_1 => x"00", -- "00"
FUNC1_ADER_2 => x"00", -- "c0"
FUNC1_ADER_3 => x"00", -- "00"
FUNC2_ADER_0 => x"00", -- A16_S "a4"
FUNC2_ADER_1 => x"00", -- "c0"
FUNC2_ADER_2 => x"00", -- "00"
FUNC2_ADER_3 => x"00", -- "00"
FUNC3_ADER_0 => x"00", -- A64_S "04"
FUNC3_ADER_1 => x"00",
FUNC3_ADER_2 => x"00",
FUNC3_ADER_3 => x"00",
FUNC4_ADER_0 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_1 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_2 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_3 => x"00", -- used for decoding the FUNC3 "c0"
FUNC5_ADER_0 => x"00",
FUNC5_ADER_1 => x"00",
FUNC5_ADER_2 => x"00",
FUNC5_ADER_3 => x"00",
FUNC6_ADER_0 => x"00",
FUNC6_ADER_1 => x"00",
FUNC6_ADER_2 => x"00",
FUNC6_ADER_3 => x"00",
IRQ_Vector => x"00", -- "00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level => x"02",
WB32bits => x"01", -- 32 bit WB of default
others => (others => '0')
);
end VME_CSR_pack;
......@@ -73,8 +73,8 @@ use work.vme64x_pack.all;
entity VME_Wb_master is
generic (
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
g_wb_data_width : integer;
g_wb_addr_width : integer
);
port (
memReq_i : in std_logic;
......
......@@ -72,10 +72,10 @@ use work.vme64x_pack.all;
entity VME_bus is
generic (
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer
);
port (
clk_i : in std_logic;
......
This diff is collapsed.
......@@ -37,9 +37,69 @@ use work.vme64x_pack.all;
entity xvme64x_core is
generic (
g_clock_freq : integer := 62500000;
g_adem_a24 : std_logic_vector(31 downto 0) := x"fff80000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_addr_width;
-- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -89,9 +149,54 @@ begin -- wrapper
U_Wrapped_VME : VME64xCore_Top
generic map (
g_adem_a32 => g_adem_a32,
g_adem_a24 => g_adem_a24,
g_clock => g_clock_freq
g_clock => g_clock_period,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f0_dawpr => g_f0_dawpr,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f1_dawpr => g_f1_dawpr,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
)
port map (
clk_i => clk_i,
......
......@@ -78,9 +78,54 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------
component xvme64x_core
generic (
g_clock_freq : integer := 62500000;
g_adem_a24 : std_logic_vector(31 downto 0) := x"fff80000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -120,27 +165,6 @@ package xvme64x_core_pkg is
);
end component xvme64x_core;
component xvme64x_core_structs is
generic (
g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64;
g_cram_size : integer := 1024;
g_window_size_a24 : std_logic_vector(31 downto 0) := x"00080000";
g_window_size_a32 : std_logic_vector(31 downto 0) := x"00080000"
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out;
vme_b : inout t_vme64x_bidir;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
);
end component xvme64x_core_structs;
end xvme64x_core_pkg;
package body xvme64x_core_pkg is
......
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