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VME64x core
Commit 72eff0ad authored by Tom Levens's avatar Tom Levens
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hdl/vme64x-core/rtl/Manifest.py
View file @ 72eff0ad
......@@ -2,12 +2,9 @@ files = [ "xvme64x_core.vhd",
"xvme64x_core_pkg.vhd",
"VME64xCore_Top.vhd",
"vme64x_pack.vhd",
"VME_Access_Decode.vhd",
"VME_Am_Match.vhd",
"VME_bus.vhd",
"VME_CR_CSR_Space.vhd",
"VME_User_CSR.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_IRQ_Controller.vhd",
"VME_swapper.vhd",
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 72eff0ad
......@@ -16,25 +16,24 @@
--
-- The main blocks:
--
-- ________________________________________________________________
-- | VME64xCore_Top.vhd |
-- |__ ____________________ __________________ |
-- | | | | | | |
-- |S | | VME_bus.vhd | | | |
-- V |A | | | |VME_to_WB_FIFO.vhd| |
-- M |M | | | | |(not implemented) | |
-- E |P | | VME | WB | | | | W
-- |L | | slave | master | | | | B
-- B |I | | | | _______ | | |
-- U |N | | | | | CSR | | | | B
-- S |G | | | | |______ | |__________________| | U
-- | | | | | | _________________ | S
-- | | | | |CRAM | | | |
-- |__| | | |______ | | IRQ_Controller | |
-- | | | | | | | |
-- | | | | CR | | | |
-- | |____________________| |_______| |_________________| |
-- |________________________________________________________________|
-- ______________________VME64xCore_Top_____________________
-- | ________________ ________ ___________________ |
-- |___ | | | | | | |
-- | | | VME Bus | | Funct | | | |
-- | | | | | Match | | VME to WB FIFO | |
-- | S | | | | | | | (not implemented) | |
-- V | A | | VME | WB | |________| | | | W
-- M | M | | slave | master | ________ | | | B
-- E | P | | | | | | | | |
-- | L | | | | | CR/CSR | | | | B
-- B | I | | | | | Space | |___________________| | U
-- U | N | | | |________| ___________________ | S
-- S | G | | | ________ | | |
-- | | | | | | | IRQ Controller | |
-- |___| | | | User | | | |
-- | | | | CSR | | | |
-- | |________________| |________| |___________________| |
-- |_________________________________________________________|
--
-- This core complies with the VME64x specifications and allows "plug and
-- play" configuration of VME crates.
......@@ -268,6 +267,8 @@ entity VME64xCore_Top is
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
-- Functions
function_o : out std_logic_vector( 3 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
......@@ -301,57 +302,86 @@ end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
signal s_reset : std_logic;
signal s_reset_n : std_logic;
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
-- signal s_VME_DATA_b : std_logic_vector(31 downto 0);
-- signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
signal s_VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DATA_DIR_VMEbus : std_logic;
signal s_VME_DATA_DIR_IRQ : std_logic;
signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0);
signal s_reset : std_logic;
signal s_reset_n : std_logic;
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
signal s_VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DATA_DIR_VMEbus : std_logic;
signal s_VME_DATA_DIR_IRQ : std_logic;
signal s_VME_IRQ_n_o : std_logic_vector( 6 downto 0);
-- CR/CSR
signal s_cr_csr_addr : std_logic_vector(18 downto 2);
signal s_cr_csr_data_o : std_logic_vector( 7 downto 0);
signal s_cr_csr_data_i : std_logic_vector( 7 downto 0);
signal s_cr_csr_we : std_logic;
signal s_f0_ader : std_logic_vector(31 downto 0);
signal s_f1_ader : std_logic_vector(31 downto 0);
signal s_f2_ader : std_logic_vector(31 downto 0);
signal s_f3_ader : std_logic_vector(31 downto 0);
signal s_f4_ader : std_logic_vector(31 downto 0);
signal s_f5_ader : std_logic_vector(31 downto 0);
signal s_f6_ader : std_logic_vector(31 downto 0);
signal s_f7_ader : std_logic_vector(31 downto 0);
signal s_module_reset : std_logic;
signal s_module_enable : std_logic;
signal s_bar : std_logic_vector( 4 downto 0);
signal s_vme_berr_n : std_logic;
signal s_irq_vector : std_logic_vector( 7 downto 0);
signal s_irq_level : std_logic_vector( 7 downto 0);
signal s_endian : std_logic_vector( 2 downto 0);
signal s_user_csr_addr : std_logic_vector(18 downto 2);
signal s_user_csr_data_i : std_logic_vector( 7 downto 0);
signal s_user_csr_data_o : std_logic_vector( 7 downto 0);
signal s_user_csr_we : std_logic;
signal s_cr_csr_addr : std_logic_vector(18 downto 2);
signal s_cr_csr_data_o : std_logic_vector( 7 downto 0);
signal s_cr_csr_data_i : std_logic_vector( 7 downto 0);
signal s_cr_csr_we : std_logic;
signal s_ader : t_ader_array(0 to 7);
signal s_module_reset : std_logic;
signal s_module_enable : std_logic;
signal s_bar : std_logic_vector( 4 downto 0);
signal s_vme_berr_n : std_logic;
signal s_irq_vector : std_logic_vector( 7 downto 0);
signal s_irq_level : std_logic_vector( 7 downto 0);
signal s_endian : std_logic_vector( 2 downto 0);
signal s_user_csr_addr : std_logic_vector(18 downto 2);
signal s_user_csr_data_i : std_logic_vector( 7 downto 0);
signal s_user_csr_data_o : std_logic_vector( 7 downto 0);
signal s_user_csr_we : std_logic;
-- Function decoders
signal s_addr_decoder_i : std_logic_vector(63 downto 0);
signal s_addr_decoder_o : std_logic_vector(63 downto 0);
signal s_decode : std_logic;
signal s_sel : std_logic;
signal s_function : std_logic_vector( 7 downto 0);
signal s_am : std_logic_vector( 5 downto 0);
signal s_xam : std_logic_vector( 7 downto 0);
-- Oversampled input signals
signal s_VME_RST_n : std_logic_vector(2 downto 0);
signal s_VME_AS_n : std_logic_vector(2 downto 0);
signal s_VME_WRITE_n : std_logic_vector(2 downto 0);
signal s_VME_DS_n : std_logic_vector(5 downto 0);
signal s_VME_IACK_n : std_logic_vector(2 downto 0);
signal s_VME_IACKIN_n : std_logic_vector(2 downto 0);
signal s_VME_RST_n : std_logic_vector(2 downto 0);
signal s_VME_AS_n : std_logic_vector(2 downto 0);
signal s_VME_WRITE_n : std_logic_vector(2 downto 0);
signal s_VME_DS_n : std_logic_vector(5 downto 0);
signal s_VME_IACK_n : std_logic_vector(2 downto 0);
signal s_VME_IACKIN_n : std_logic_vector(2 downto 0);
-- CR/CSR parameter arrays
-- ADEM array has an extra index (-1) to simplify looping while checking the
-- EFM bit of the previous function.
constant c_ADEM : t_adem_array(-1 to 7) := (
x"0000_0000",
g_F0_ADEM, g_F1_ADEM, g_F2_ADEM, g_F3_ADEM,
g_F4_ADEM, g_F5_ADEM, g_F6_ADEM, g_F7_ADEM
);
constant c_AMCAP : t_amcap_array(0 to 7) := (
g_F0_AMCAP, g_F1_AMCAP, g_F2_AMCAP, g_F3_AMCAP,
g_F4_AMCAP, g_F5_AMCAP, g_F6_AMCAP, g_F7_AMCAP
);
constant c_XAMCAP : t_xamcap_array(0 to 7) := (
g_F0_XAMCAP, g_F1_XAMCAP, g_F2_XAMCAP, g_F3_XAMCAP,
g_F4_XAMCAP, g_F5_XAMCAP, g_F6_XAMCAP, g_F7_XAMCAP
);
constant c_DAWPR : t_dawpr_array(0 to 7) := (
g_F0_DAWPR, g_F1_DAWPR, g_F2_DAWPR, g_F3_DAWPR,
g_F4_DAWPR, g_F5_DAWPR, g_F6_DAWPR, g_F7_DAWPR
);
signal s_faf_ader : t_ader_array(0 to 7);
signal s_dfs_adem : t_adem_array(0 to 7);
begin
s_faf_ader <= (f0_faf_ader_i, f1_faf_ader_i, f2_faf_ader_i, f3_faf_ader_i,
f4_faf_ader_i, f5_faf_ader_i, f6_faf_ader_i, f7_faf_ader_i);
s_dfs_adem <= (f0_dfs_adem_i, f1_dfs_adem_i, f2_dfs_adem_i, f3_dfs_adem_i,
f4_dfs_adem_i, f5_dfs_adem_i, f6_dfs_adem_i, f7_dfs_adem_i);
------------------------------------------------------------------------------
-- Metastability
------------------------------------------------------------------------------
......@@ -378,37 +408,7 @@ begin
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH
)
port map (
clk_i => clk_i,
......@@ -450,19 +450,20 @@ begin
rty_i => RTY_i,
stall_i => STALL_i,
-- Function decoder
addr_decoder_i => s_addr_decoder_o,
addr_decoder_o => s_addr_decoder_i,
decode_o => s_decode,
am_o => s_am,
xam_o => s_xam,
sel_i => s_sel,
function_i => s_function,
-- CR/CSR signals
cr_csr_addr_o => s_cr_csr_addr,
cr_csr_data_i => s_cr_csr_data_o,
cr_csr_data_o => s_cr_csr_data_i,
cr_csr_we_o => s_cr_csr_we,
f0_ader_i => s_f0_ader,
f1_ader_i => s_f1_ader,
f2_ader_i => s_f2_ader,
f3_ader_i => s_f3_ader,
f4_ader_i => s_f4_ader,
f5_ader_i => s_f5_ader,
f6_ader_i => s_f6_ader,
f7_ader_i => s_f7_ader,
endian_i => s_endian,
module_enable_i => s_module_enable,
bar_i => s_bar
......@@ -475,6 +476,31 @@ begin
VME_BERR_o <= not s_vme_berr_n; -- The VME_BERR is asserted when '1' because
-- the buffers on the board invert the logic.
Inst_VME_Funct_Match : VME_Funct_Match
generic map (
g_ADEM => c_ADEM,
g_AMCAP => c_AMCAP,
g_XAMCAP => c_XAMCAP
)
port map (
clk_i => clk_i,
rst_n_i => s_reset_n,
addr_i => s_addr_decoder_i,
addr_o => s_addr_decoder_o,
decode_i => s_decode,
am_i => s_am,
xam_i => s_xam,
ader_i => s_ader,
dfs_adem_i => s_dfs_adem,
sel_o => s_sel,
function_o => s_function
);
function_o <= s_function;
------------------------------------------------------------------------------
-- Output
------------------------------------------------------------------------------
......@@ -529,51 +555,23 @@ begin
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F0_DAWPR => g_F0_DAWPR,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F1_DAWPR => g_F1_DAWPR,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F2_DAWPR => g_F2_DAWPR,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F3_DAWPR => g_F3_DAWPR,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F4_DAWPR => g_F4_DAWPR,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F5_DAWPR => g_F5_DAWPR,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F6_DAWPR => g_F6_DAWPR,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP,
g_F7_DAWPR => g_F7_DAWPR
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_ADEM => c_ADEM,
g_AMCAP => c_AMCAP,
g_XAMCAP => c_XAMCAP,
g_DAWPR => c_DAWPR
)
port map (
clk_i => clk_i,
......@@ -600,32 +598,9 @@ begin
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
f0_ader_o => s_f0_ader,
f1_ader_o => s_f1_ader,
f2_ader_o => s_f2_ader,
f3_ader_o => s_f3_ader,
f4_ader_o => s_f4_ader,
f5_ader_o => s_f5_ader,
f6_ader_o => s_f6_ader,
f7_ader_o => s_f7_ader,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
ader_o => s_ader,
faf_ader_i => s_faf_ader,
dfs_adem_i => s_dfs_adem
);
-- User CSR space
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd deleted 100644 → 0
View file @ a3b2fde3
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Access_Decode (VME_Access_Decode.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This component checks if the board is addressed and if it is, allows
-- the access to CR/CSR space by asserting the Confaccess signal, or allows
-- the access to WB bus by asserting the CardSel signal.
--
-- The access to CR/CSR space is possible if:
-- 1) Addr[23:19] = BAR[7:3], (BAR[7:3] = not VME_GA_i = not Slot number)
-- 2) AM = 0x2f
-- 3) The initialization is finished (wait about 8800 ns after power-up or
-- software reset)
--
-- To Access the Wb bus we have 7 functions; only one at time can be selected.
-- If one of these functions is selected the CardSel signal is asserted (this
-- is the responding Slave). To access the Wb bus we need to decode the AM and
-- the address lines; so as shown in the block diagram the main components are
-- two: VME_Funct_Match, VME_Am_Match.
--
-- ___________________________________________
-- | VME_Access_Decode.vhd |
-- | |
-- | ____________ ____________ |
-- | | | | | |
-- | | FUNCTION | | AM | |
-- | | | | | |
-- | | MATCH | | MATCH | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | |____________| |____________| |
-- | |
-- |___________________________________________|
--
-- Each function has one ADER, one ADEM, one AMCAP and one XAMCAP register.
-- The ADEM, AMCAP, XAMCAP are in the CR memory; the Master can't write these
-- registers. The ADER registers are located in the CSR space so the VME
-- master has to write these registers properly after the initialization.
--
-- How to access:
--
-- ADER[31:8] --> compare bits (put here the base address)
-- [7:2] --> AM
-- [1] --> '0'
-- [0] --> XAM bit: '0'; '1' only for 2e access mode
--
-- If XAM is '1' it will be:
--
-- ADER[31:10] --> compare bits (put here the base address)
-- [9:2] --> XAM
-- [1] --> '0'
-- [0] --> '1'
--
-- ADEM[31:8] --> mask bits
-- [7:4] --> "0000"
-- [3] --> '0' --> The ADER is programmable
-- [2] --> DFS
-- [1] --> '0'
-- [0] --> EFM
--
-- EFM = Extra Function Mask: if '1' the next ADEM (and so the next AMCAP,
-- XAMCAP and ADER) provides the upper bit's mask for a 64 bit decoder.
-- This bit is '1' during A64 and 2e access.
-- DFS = Dynamic Function Decoder: a '1' here means this function can be
-- used to decode different address length (eg. A16 or A24 or A32) so
-- the mask bits should be all '1'.
--
-- AMCAP[63:0]
-- 6 AM lines --> 2**6 = 64 different configurations
-- This register is 64 bits wide and each bit rappresents one AM
-- configuration. If the bit is '1' it means that the corresponding AM is
-- supported by this function.
-- If the corresponding ADEM's DFS is 0, only the AMCAP's bits with the
-- same address width must be '1'.
-- If the corresponding ADEM's DFS is 1, one or more AMCAP's bits can be
-- '1'
-- eg: "1011101100000000001000100000000100000000000000001011101100000000"
-- this function supports the following access mode: A24_S, A24_BLT,
-- A24_MBLT, A16_S, A32_S, A32_BLT, A32_MBLT supervisor and user access
--
-- XAMCAP[255:0]
-- 8 XAM lines --> 2**8 = 256 different configurations
-- This register is 256 bits wide and each bit rappresents one XAM
-- configuration. If the bit is '1' it means that the corresponding XAM is
-- supported by this function.
-- This register is used during the decode phase if the XAM bit is
-- asserted (1).
--
-- Before accessing the board the VME Master must write the ADER registers. Of
-- course for writing properly the ADER the VME Master needs to know the
-- corresponding ADEM and check if EFM or DFS bits are asserted. The VME
-- Master can read also the AMCAP and XAMCAP and check the access mode
-- supported by each function.
--
-- eg.1 let's imagine that we want to access different storage device; we can
-- assign one base address and one function at each storage.
-- Now the VME Master has to write the base address of each storage in the
-- corresponding ADER's compare bits and after this operation each function
-- decodes the access to the corresponding storage.
-- eg.2 this example is relative to our application; the vme64x interface has
-- to transfer data from the VMEbus to WB bus and in this core we have only
-- one WB master. We can use the same base address for all the functions
-- because we will access always the same WB master, and use the different
-- functions to access with different mode eg:
-- function0 --> A32_S, A32_BLT, A32_MBLT modes
-- function1 --> A24_S, A24_BLT, A24_MBLT modes
-- function2 --> A16 mode
-- function3 and function4 --> A64, A64_BLT, A64_MBLT
-- function5 and function6 --> 2eVME and 2eSST modes
-- Note that if the address is 64 bits wide we need of two ADER and two ADEM
-- to decode the address so we need two functions. (see also EFM
-- bit definition) Of course you can mix these two example and set up one
-- system with more storage devices each with its base address and to assign
-- each storage more than one function to access it with all the access modes.
-- It is also possible extend the number of the functions defining other ADEM,
-- AMCAP, XAMCAP and ADER in the User CR Space and User CSR Space (see the
-- VME_CR_CSR_Space.vhd component) respectively.
-- In the VME_Funct_Match.vhd and VME_Am_Match.vhd components you can find
-- more detailsabout the decode process.
--
-- To access the board both the FunctMatch(i) and AmMatch(i) must be equal to
-- one.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_Access_Decode is
port (
clk_i : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
decode : in std_logic;
ModuleEnable : in std_logic;
Addr : in std_logic_vector(63 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
BAR_i : in std_logic_vector(4 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Funct_Sel : out std_logic_vector(7 downto 0);
Base_Addr : out std_logic_vector(63 downto 0);
Confaccess : out std_logic;
CardSel : out std_logic
);
end VME_Access_Decode;
architecture Behavioral of VME_Access_Decode is
signal s_Func_Match : std_logic_vector(7 downto 0);
signal s_Am_Match : std_logic_vector(7 downto 0);
signal s_nx_base_addr : std_logic_vector(63 downto 0);
signal s_func_sel : std_logic_vector(7 downto 0);
signal s_DFS : std_logic_vector(7 downto 0);
begin
Funct_Sel <= s_func_sel;
Inst_Funct_Match: VME_Funct_Match
port map (
clk_i => clk_i,
reset => reset,
decode => decode,
mainFSMreset => mainFSMreset,
Addr => Addr,
AddrWidth => AddrWidth,
Ader0 => Ader0,
Ader1 => Ader1,
Ader2 => Ader2,
Ader3 => Ader3,
Ader4 => Ader4,
Ader5 => Ader5,
Ader6 => Ader6,
Ader7 => Ader7,
Adem0 => Adem0,
Adem1 => Adem1,
Adem2 => Adem2,
Adem3 => Adem3,
Adem4 => Adem4,
Adem5 => Adem5,
Adem6 => Adem6,
Adem7 => Adem7,
FunctMatch => s_Func_Match,
DFS_o => s_DFS,
Nx_Base_Addr => s_nx_base_addr
);
Inst_Am_Match: VME_Am_Match
port map (
clk_i => clk_i,
reset => reset,
mainFSMreset => mainFSMreset,
Ader0 => Ader0,
Ader1 => Ader1,
Ader2 => Ader2,
Ader3 => Ader3,
Ader4 => Ader4,
Ader5 => Ader5,
Ader6 => Ader6,
Ader7 => Ader7,
AmCap0 => AmCap0,
AmCap1 => AmCap1,
AmCap2 => AmCap2,
AmCap3 => AmCap3,
AmCap4 => AmCap4,
AmCap5 => AmCap5,
AmCap6 => AmCap6,
AmCap7 => AmCap7,
XAmCap0 => XAmCap0,
XAmCap1 => XAmCap1,
XAmCap2 => XAmCap2,
XAmCap3 => XAmCap3,
XAmCap4 => XAmCap4,
XAmCap5 => XAmCap5,
XAmCap6 => XAmCap6,
XAmCap7 => XAmCap7,
Am => Am,
XAm => XAm,
DFS_i => s_DFS,
decode => decode,
AmMatch => s_Am_Match
);
-- Check if the WB application is addressed
process (clk_i)
begin
if rising_edge(clk_i) then
CardSel <= '0';
Base_Addr <= (others => '0');
if ModuleEnable = '1' then
for I in 0 to 7 loop
if s_func_sel(i) = '1' then
CardSel <= '1';
Base_Addr <= s_nx_base_addr;
-- exit; in this case the exit statement is useless
end if;
end loop;
end if;
end if;
end process;
s_func_sel <= s_Func_Match and s_Am_Match;
-- Check if the CR/CSR space is addressed
Confaccess <= '1'
when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_AM_CR_CSR
else '0';
end Behavioral;
hdl/vme64x-core/rtl/VME_Am_Match.vhd deleted 100644 → 0
View file @ a3b2fde3
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Am_Match (VME_Am_Match.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This component checks if the AM match. If it is the correspondent AmMatch's
-- bit is asserted. This condition is necessary but not sufficient to select
-- the function and access the board.
--
-- If DFS = '0' the function supports only access modes with the same address
-- width;
-- 1 function --> only 1 address width;
-- with address width I mean A16, A24, A32 or A64.
-- is sufficient check the AMCAP;
-- AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
--
-- If DFS = '1' the function supports access modes with different address
-- widths so AmMatch(i) is asserted only if ADER[7:2] = AM and
-- s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
--
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if
-- AM = 0x20 and if the -- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if
-- DFS = '1' also ADER[9:2] must be equal -- to XAM[7:0] lines.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_Am_Match is
port (
clk_i : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
decode : in std_logic;
AmMatch : out std_logic_vector(7 downto 0)
);
end VME_Am_Match;
architecture Behavioral of VME_Am_Match is
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
begin
s_FUNC_ADER(0) <= unsigned(Ader0);
s_FUNC_ADER(1) <= unsigned(Ader1);
s_FUNC_ADER(2) <= unsigned(Ader2);
s_FUNC_ADER(3) <= unsigned(Ader3);
s_FUNC_ADER(4) <= unsigned(Ader4);
s_FUNC_ADER(5) <= unsigned(Ader5);
s_FUNC_ADER(6) <= unsigned(Ader6);
s_FUNC_ADER(7) <= unsigned(Ader7);
s_FUNC_AMCAP(0) <= unsigned(AmCap0);
s_FUNC_AMCAP(1) <= unsigned(AmCap1);
s_FUNC_AMCAP(2) <= unsigned(AmCap2);
s_FUNC_AMCAP(3) <= unsigned(AmCap3);
s_FUNC_AMCAP(4) <= unsigned(AmCap4);
s_FUNC_AMCAP(5) <= unsigned(AmCap5);
s_FUNC_AMCAP(6) <= unsigned(AmCap6);
s_FUNC_AMCAP(7) <= unsigned(AmCap7);
s_FUNC_XAMCAP(0) <= unsigned(XAmCap0);
s_FUNC_XAMCAP(1) <= unsigned(XAmCap1);
s_FUNC_XAMCAP(2) <= unsigned(XAmCap2);
s_FUNC_XAMCAP(3) <= unsigned(XAmCap3);
s_FUNC_XAMCAP(4) <= unsigned(XAmCap4);
s_FUNC_XAMCAP(5) <= unsigned(XAmCap5);
s_FUNC_XAMCAP(6) <= unsigned(XAmCap6);
s_FUNC_XAMCAP(7) <= unsigned(XAmCap7);
p_AMmatch: process(clk_i) begin
if rising_edge(clk_i) then
if mainFSMreset = '1' or reset = '1' then
AmMatch <= (others => '0');
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
else
if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
end if;
else
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
end if;
end if;
end loop;
end if;
end if;
end process;
-- Check if the AM is in the AMCAP register
process (s_FUNC_AMCAP, Am) begin
s_amcap_match <= (others => '0');
for i in 0 to 7 loop
s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am)));
end loop;
end process;
-- Check if the XAM is in the XAMCAP register
process (s_FUNC_XAMCAP, XAm) begin
s_xamcap_match <= (others => '0');
for i in 0 to 7 loop
s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(unsigned(XAm)));
end loop;
end process;
end Behavioral;
hdl/vme64x-core/rtl/VME_CRAM.vhd deleted 100644 → 0
View file @ a3b2fde3
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CRAM (VME_CRAM.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: CRAM memory
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_CRAM is
generic (
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0)
);
port (
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0)
);
end VME_CRAM;
architecture rtl of VME_CRAM is
type t_cram is array (f_size(g_BEG_CRAM, g_END_CRAM)-1 downto 0)
of std_logic_vector(7 downto 0);
signal s_cram : t_cram;
signal s_addr : unsigned(18 downto 2);
signal s_addr_1 : unsigned(18 downto 2);
begin
s_addr <= unsigned(addr_i(18 downto 2));
process (clk_i) begin
if rising_edge(clk_i) then
if we_i = '1' then
s_cram(to_integer(s_addr)) <= data_i;
end if;
s_addr_1 <= s_addr;
end if;
end process;
data_o <= s_cram(to_integer(s_addr_1));
end rtl;
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 72eff0ad
......@@ -122,38 +122,10 @@ entity VME_CR_CSR_Space is
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F0_DAWPR : std_logic_vector( 7 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F1_DAWPR : std_logic_vector( 7 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F2_DAWPR : std_logic_vector( 7 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F3_DAWPR : std_logic_vector( 7 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F4_DAWPR : std_logic_vector( 7 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F5_DAWPR : std_logic_vector( 7 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F6_DAWPR : std_logic_vector( 7 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0);
g_F7_DAWPR : std_logic_vector( 7 downto 0)
g_ADEM : t_adem_array(-1 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7);
g_DAWPR : t_dawpr_array(0 to 7)
);
port (
clk_i : in std_logic;
......@@ -180,88 +152,149 @@ entity VME_CR_CSR_Space is
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
f0_ader_o : out std_logic_vector(31 downto 0);
f1_ader_o : out std_logic_vector(31 downto 0);
f2_ader_o : out std_logic_vector(31 downto 0);
f3_ader_o : out std_logic_vector(31 downto 0);
f4_ader_o : out std_logic_vector(31 downto 0);
f5_ader_o : out std_logic_vector(31 downto 0);
f6_ader_o : out std_logic_vector(31 downto 0);
f7_ader_o : out std_logic_vector(31 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0);
f1_faf_ader_i : in std_logic_vector(31 downto 0);
f2_faf_ader_i : in std_logic_vector(31 downto 0);
f3_faf_ader_i : in std_logic_vector(31 downto 0);
f4_faf_ader_i : in std_logic_vector(31 downto 0);
f5_faf_ader_i : in std_logic_vector(31 downto 0);
f6_faf_ader_i : in std_logic_vector(31 downto 0);
f7_faf_ader_i : in std_logic_vector(31 downto 0);
f0_dfs_adem_i : in std_logic_vector(31 downto 0);
f1_dfs_adem_i : in std_logic_vector(31 downto 0);
f2_dfs_adem_i : in std_logic_vector(31 downto 0);
f3_dfs_adem_i : in std_logic_vector(31 downto 0);
f4_dfs_adem_i : in std_logic_vector(31 downto 0);
f5_dfs_adem_i : in std_logic_vector(31 downto 0);
f6_dfs_adem_i : in std_logic_vector(31 downto 0);
f7_dfs_adem_i : in std_logic_vector(31 downto 0)
ader_o : out t_ader_array(0 to 7);
faf_ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7)
);
end VME_CR_CSR_Space;
architecture rtl of VME_CR_CSR_Space is
signal s_addr : unsigned(18 downto 2);
signal s_addr : unsigned(18 downto 2);
signal s_ga_parity : std_logic;
signal s_reg_bar : std_logic_vector(7 downto 0);
signal s_reg_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_ader : t_ader_array(0 to 7);
signal s_ader : t_ader_array(0 to 7);
-- CR/CSR
signal s_cr_access : std_logic;
signal s_csr_access : std_logic;
signal s_cram_access : std_logic;
signal s_user_cr_access : std_logic;
signal s_user_csr_access : std_logic;
signal s_cr_data : std_logic_vector(7 downto 0);
signal s_csr_data : std_logic_vector(7 downto 0);
-- Function to calculate the size of a CR/CSR area
function f_size (s, e : std_logic_vector) return integer is
begin
return ((to_integer(unsigned(e)) - to_integer(unsigned(s))) / 4) + 1;
end;
signal s_ga_parity : std_logic;
-- User CR/CSR and CRAM enabled when size of area greater than 1
constant c_CRAM_SIZE : integer := f_size(g_BEG_CRAM, g_END_CRAM);
constant c_CRAM_ENA : boolean := c_CRAM_SIZE > 1;
signal s_cr_access : std_logic;
signal s_csr_access : std_logic;
signal s_cram_access : std_logic;
signal s_user_cr_access : std_logic;
signal s_user_csr_access : std_logic;
constant c_USER_CR_SIZE : integer := f_size(g_BEG_USER_CR, g_END_USER_CR);
constant c_USER_CR_ENA : boolean := c_USER_CR_SIZE > 1;
signal s_cr_data : std_logic_vector(7 downto 0);
signal s_csr_data : std_logic_vector(7 downto 0);
signal s_cram_data : std_logic_vector(7 downto 0);
constant c_USER_CSR_SIZE : integer := f_size(g_BEG_USER_CSR, g_END_USER_CSR);
constant c_USER_CSR_ENA : boolean := c_USER_CSR_SIZE > 1;
signal s_cram_addr : std_logic_vector(18 downto 2);
signal s_cram_we : std_logic;
-- CRAM
type t_cram is array (c_CRAM_SIZE-1 downto 0) of std_logic_vector(7 downto 0);
signal s_cram : t_cram;
signal s_cram_data : std_logic_vector(7 downto 0);
signal s_cram_waddr : unsigned(18 downto 2);
signal s_cram_raddr : unsigned(18 downto 2);
signal s_cram_we : std_logic;
-- Addresses
constant c_BEG_CR : unsigned(18 downto 2) := to_unsigned(16#00000#/4, 17);
constant c_END_CR : unsigned(18 downto 2) := to_unsigned(16#00fff#/4, 17);
constant c_BEG_CSR : unsigned(18 downto 2) := to_unsigned(16#7ff60#/4, 17);
constant c_END_CSR : unsigned(18 downto 2) := to_unsigned(16#7ffff#/4, 17);
constant c_BEG_USER_CR : unsigned(18 downto 2) := unsigned(g_BEG_USER_CR(18 downto 2));
constant c_END_USER_CR : unsigned(18 downto 2) := unsigned(g_END_USER_CR(18 downto 2));
constant c_BEG_USER_CSR : unsigned(18 downto 2) := unsigned(g_BEG_USER_CSR(18 downto 2));
constant c_END_USER_CSR : unsigned(18 downto 2) := unsigned(g_END_USER_CSR(18 downto 2));
constant c_BEG_CRAM : unsigned(18 downto 2) := unsigned(g_BEG_CRAM(18 downto 2));
constant c_END_CRAM : unsigned(18 downto 2) := unsigned(g_END_CRAM(18 downto 2));
constant c_BAR_REG : integer := 16#7ffff#/4;
constant c_BIT_SET_REG : integer := 16#7fffb#/4;
constant c_BIT_CLR_REG : integer := 16#7fff7#/4;
constant c_CRAM_OWNER_REG : integer := 16#7fff3#/4;
constant c_USR_SET_REG : integer := 16#7ffef#/4;
constant c_USR_CLR_REG : integer := 16#7ffeb#/4;
constant c_ADER_REG_END : integer := 16#7ffdf#/4;
constant c_ADER_REG_BEG : integer := 16#7ff63#/4;
-- Indexes in bit set/clr register
constant c_RESET_BIT : integer := 7;
constant c_SYSFAIL_EN_BIT : integer := 6;
constant c_FAILED_BIT : integer := 5;
constant c_ENABLE_BIT : integer := 4;
constant c_BERR_BIT : integer := 3;
constant c_CRAM_OWNER_BIT : integer := 2;
-- Value for unused memory locations
constant c_UNUSED : std_logic_vector(7 downto 0) := x"ff";
signal s_reg_bar : std_logic_vector(7 downto 0);
signal s_reg_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
------------------------------------------------------------------------------
-- Generate configuration ROM
------------------------------------------------------------------------------
type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
type t_reg_array is array (integer range <>) of std_logic_vector(31 downto 0);
-- Function to generate a CR sub-array from a std_logic_vector
function f_cr_vec (v : std_logic_vector) return t_cr_array is
variable a : t_cr_array(0 to v'length/8-1);
begin
for i in 0 to a'length-1 loop
a(i) := v(v'length-(i*8)-1 downto v'length-(i*8)-8);
end loop;
return a;
end function;
signal s_reg_ader : t_reg_array(0 to 7);
signal s_ader : t_reg_array(0 to 7);
signal s_faf_ader : t_reg_array(0 to 7);
signal s_dfs_adem : t_reg_array(0 to 7);
-- Function to encode the configuration ROM
function f_cr_encode return t_cr_array is
variable cr : t_cr_array(0 to 1023) := (others => x"00");
variable crc : unsigned(7 downto 0) := x"00";
begin
cr(16#001# to 16#003#) := (x"00", x"03", x"ff"); -- Length of CR (excluding checksum)
cr(16#004#) := x"81"; -- CR data access width
cr(16#005#) := x"81"; -- CSR data access width
cr(16#006#) := x"02"; -- CR/CSR space specification ID
cr(16#007#) := x"43"; -- ASCII "C"
cr(16#008#) := x"52"; -- ASCII "R"
cr(16#009# to 16#00b#) := f_cr_vec(g_MANUFACTURER_ID); -- Manufacturer ID
cr(16#00c# to 16#00f#) := f_cr_vec(g_BOARD_ID); -- Board ID
cr(16#010# to 16#013#) := f_cr_vec(g_REVISION_ID); -- Revision ID
cr(16#014# to 16#016#) := f_cr_vec(g_ASCII_PTR); -- Pointer to an ASCII string
cr(16#01f#) := g_PROGRAM_ID; -- Program ID
cr(16#020# to 16#022#) := f_cr_vec(g_BEG_USER_CR); -- Beg user CR
cr(16#023# to 16#025#) := f_cr_vec(g_END_USER_CR); -- End user CR
cr(16#026# to 16#028#) := f_cr_vec(g_BEG_CRAM); -- Beg CRAM
cr(16#029# to 16#02b#) := f_cr_vec(g_END_CRAM); -- End CRAM
cr(16#02c# to 16#02e#) := f_cr_vec(g_BEG_USER_CSR); -- Beg user CSR
cr(16#02f# to 16#031#) := f_cr_vec(g_END_USER_CSR); -- End user CSR
cr(16#032# to 16#034#) := f_cr_vec(g_BEG_SN); -- Beg serial number
cr(16#035# to 16#037#) := f_cr_vec(g_END_SN); -- End serial number
cr(16#038#) := x"04"; -- Slave characteristics parameter
cr(16#039#) := x"00"; -- User-defined slave char. param.
cr(16#03d#) := x"0e"; -- Interrupter capabilities
cr(16#03f#) := x"81"; -- CRAM data access width
for i in 0 to 7 loop
cr(16#040#+i) := g_DAWPR(i); -- Function X DAWPR
cr(16#048#+i*8 to 16#04f#+i*8) := f_cr_vec(g_AMCAP(i)); -- Function X AMCAP
cr(16#088#+i*32 to 16#0a7#+i*32) := f_cr_vec(g_XAMCAP(i)); -- Function X XAMCAP
cr(16#188#+i*4 to 16#18b#+i*4) := f_cr_vec(g_ADEM(i)); -- Function X ADEM
end loop;
for i in 1 to cr'length-1 loop
crc := crc + unsigned(cr(i));
end loop;
cr(16#000#) := std_logic_vector(crc); -- Checksum
return cr;
end;
constant c_ADEM : t_reg_array(-1 to 7) := (
x"00000000",
g_F0_ADEM, g_F1_ADEM, g_F2_ADEM, g_F3_ADEM,
g_F4_ADEM, g_F5_ADEM, g_F6_ADEM, g_F7_ADEM
);
signal s_cr_rom : t_cr_array(0 to 1023) := f_cr_encode;
signal s_cr_rom : t_cr_array(1023 downto 0) := f_vme_cr_encode(
g_MANUFACTURER_ID, g_BOARD_ID, g_REVISION_ID, g_PROGRAM_ID,
g_ASCII_PTR,
g_BEG_USER_CR, g_END_USER_CR,
g_BEG_CRAM, g_END_CRAM,
g_BEG_USER_CSR, g_END_USER_CSR,
g_BEG_SN, g_END_SN,
g_F0_ADEM, g_F0_AMCAP, g_F0_XAMCAP, g_F0_DAWPR,
g_F1_ADEM, g_F1_AMCAP, g_F1_XAMCAP, g_F1_DAWPR,
g_F2_ADEM, g_F2_AMCAP, g_F2_XAMCAP, g_F2_DAWPR,
g_F3_ADEM, g_F3_AMCAP, g_F3_XAMCAP, g_F3_DAWPR,
g_F4_ADEM, g_F4_AMCAP, g_F4_XAMCAP, g_F4_DAWPR,
g_F5_ADEM, g_F5_AMCAP, g_F5_XAMCAP, g_F5_DAWPR,
g_F6_ADEM, g_F6_AMCAP, g_F6_XAMCAP, g_F6_DAWPR,
g_F7_ADEM, g_F7_AMCAP, g_F7_XAMCAP, g_F7_DAWPR
);
------------------------------------------------------------------------------
begin
......@@ -270,8 +303,8 @@ begin
------------------------------------------------------------------------------
-- Defined CR
------------------------------------------------------------------------------
s_cr_access <= '1' when s_addr >= c_BEG_CR(18 downto 2) and
s_addr <= c_END_CR(18 downto 2)
s_cr_access <= '1' when s_addr >= c_BEG_CR and
s_addr <= c_END_CR
else '0';
process (clk_i)
......@@ -284,8 +317,8 @@ begin
------------------------------------------------------------------------------
-- Defined CSR
------------------------------------------------------------------------------
s_csr_access <= '1' when s_addr >= c_BEG_CSR(18 downto 2) and
s_addr <= c_END_CSR(18 downto 2)
s_csr_access <= '1' when s_addr >= c_BEG_CSR and
s_addr <= c_END_CSR
else '0';
-- If the crate is not driving the GA lines or the parity is even the BAR
......@@ -295,6 +328,9 @@ begin
-- Write
process (clk_i)
variable v_addr : unsigned(6 downto 2);
variable v_index : integer;
variable v_byte : integer;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
......@@ -309,171 +345,134 @@ begin
s_reg_ader <= (others => x"00000000");
else
if we_i = '1' and s_csr_access = '1' then
case s_addr is
when c_ADDR_BAR(18 downto 2) =>
case to_integer(s_addr) is
when c_BAR_REG =>
s_reg_bar <= data_i;
when c_ADDR_BIT_SET_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) or data_i(i);
end loop;
when c_BIT_SET_REG =>
s_reg_bit_reg <= s_reg_bit_reg or data_i;
when c_ADDR_BIT_CLR_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) and (not data_i(i));
end loop;
if data_i(2) = '1' then
when c_BIT_CLR_REG =>
s_reg_bit_reg <= s_reg_bit_reg and not data_i;
if data_i(c_CRAM_OWNER_BIT) = '1' then
s_reg_cram_owner <= x"00";
end if;
when c_ADDR_CRAM_OWNER(18 downto 2) =>
when c_CRAM_OWNER_REG =>
if s_reg_cram_owner = x"00" then
s_reg_cram_owner <= data_i;
s_reg_bit_reg(2) <= '1';
s_reg_bit_reg(c_CRAM_OWNER_BIT) <= '1';
end if;
when c_ADDR_USR_SET_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) or data_i(i);
end loop;
when c_ADDR_USR_CLR_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) and (not data_i(i));
end loop;
when c_ADDR_F7_ADER_0(18 downto 2) => s_reg_ader(7)( 7 downto 0) <= data_i;
when c_ADDR_F7_ADER_1(18 downto 2) => s_reg_ader(7)(15 downto 8) <= data_i;
when c_ADDR_F7_ADER_2(18 downto 2) => s_reg_ader(7)(23 downto 16) <= data_i;
when c_ADDR_F7_ADER_3(18 downto 2) => s_reg_ader(7)(31 downto 24) <= data_i;
when c_ADDR_F6_ADER_0(18 downto 2) => s_reg_ader(6)( 7 downto 0) <= data_i;
when c_ADDR_F6_ADER_1(18 downto 2) => s_reg_ader(6)(15 downto 8) <= data_i;
when c_ADDR_F6_ADER_2(18 downto 2) => s_reg_ader(6)(23 downto 16) <= data_i;
when c_ADDR_F6_ADER_3(18 downto 2) => s_reg_ader(6)(31 downto 24) <= data_i;
when c_ADDR_F5_ADER_0(18 downto 2) => s_reg_ader(5)( 7 downto 0) <= data_i;
when c_ADDR_F5_ADER_1(18 downto 2) => s_reg_ader(5)(15 downto 8) <= data_i;
when c_ADDR_F5_ADER_2(18 downto 2) => s_reg_ader(5)(23 downto 16) <= data_i;
when c_ADDR_F5_ADER_3(18 downto 2) => s_reg_ader(5)(31 downto 24) <= data_i;
when c_ADDR_F4_ADER_0(18 downto 2) => s_reg_ader(4)( 7 downto 0) <= data_i;
when c_ADDR_F4_ADER_1(18 downto 2) => s_reg_ader(4)(15 downto 8) <= data_i;
when c_ADDR_F4_ADER_2(18 downto 2) => s_reg_ader(4)(23 downto 16) <= data_i;
when c_ADDR_F4_ADER_3(18 downto 2) => s_reg_ader(4)(31 downto 24) <= data_i;
when c_ADDR_F3_ADER_0(18 downto 2) => s_reg_ader(3)( 7 downto 0) <= data_i;
when c_ADDR_F3_ADER_1(18 downto 2) => s_reg_ader(3)(15 downto 8) <= data_i;
when c_ADDR_F3_ADER_2(18 downto 2) => s_reg_ader(3)(23 downto 16) <= data_i;
when c_ADDR_F3_ADER_3(18 downto 2) => s_reg_ader(3)(31 downto 24) <= data_i;
when c_ADDR_F2_ADER_0(18 downto 2) => s_reg_ader(2)( 7 downto 0) <= data_i;
when c_ADDR_F2_ADER_1(18 downto 2) => s_reg_ader(2)(15 downto 8) <= data_i;
when c_ADDR_F2_ADER_2(18 downto 2) => s_reg_ader(2)(23 downto 16) <= data_i;
when c_ADDR_F2_ADER_3(18 downto 2) => s_reg_ader(2)(31 downto 24) <= data_i;
when c_ADDR_F1_ADER_0(18 downto 2) => s_reg_ader(1)( 7 downto 0) <= data_i;
when c_ADDR_F1_ADER_1(18 downto 2) => s_reg_ader(1)(15 downto 8) <= data_i;
when c_ADDR_F1_ADER_2(18 downto 2) => s_reg_ader(1)(23 downto 16) <= data_i;
when c_ADDR_F1_ADER_3(18 downto 2) => s_reg_ader(1)(31 downto 24) <= data_i;
when c_ADDR_F0_ADER_0(18 downto 2) => s_reg_ader(0)( 7 downto 0) <= data_i;
when c_ADDR_F0_ADER_1(18 downto 2) => s_reg_ader(0)(15 downto 8) <= data_i;
when c_ADDR_F0_ADER_2(18 downto 2) => s_reg_ader(0)(23 downto 16) <= data_i;
when c_ADDR_F0_ADER_3(18 downto 2) => s_reg_ader(0)(31 downto 24) <= data_i;
when others => null;
when c_USR_SET_REG =>
s_reg_usr_bit_reg <= s_reg_usr_bit_reg or data_i;
when c_USR_CLR_REG =>
s_reg_usr_bit_reg <= s_reg_usr_bit_reg and not data_i;
when c_ADER_REG_BEG to c_ADER_REG_END =>
v_addr := s_addr(6 downto 2) - to_unsigned(c_ADER_REG_BEG, 5);
v_index := to_integer(v_addr(6 downto 4));
v_byte := 3-to_integer(v_addr(3 downto 2));
s_reg_ader(v_index)(8*v_byte+7 downto 8*v_byte) <= data_i;
when others =>
null;
end case;
end if;
if vme_berr_n_i = '0' then
s_reg_bit_reg(3) <= '1';
s_reg_bit_reg(c_BERR_BIT) <= '1';
end if;
if vme_sysfail_i = '1' then
s_reg_bit_reg(5) <= '1';
s_reg_bit_reg(c_FAILED_BIT) <= '1';
end if;
end if;
end if;
end process;
bar_o <= s_reg_bar(7 downto 3);
f0_ader_o <= s_ader(0) when s_ader(0)(c_ADER_DFSR) = '0' else (others => '0');
f1_ader_o <= s_ader(1) when s_ader(1)(c_ADER_DFSR) = '0' else (others => '0');
f2_ader_o <= s_ader(2) when s_ader(2)(c_ADER_DFSR) = '0' else (others => '0');
f3_ader_o <= s_ader(3) when s_ader(3)(c_ADER_DFSR) = '0' else (others => '0');
f4_ader_o <= s_ader(4) when s_ader(4)(c_ADER_DFSR) = '0' else (others => '0');
f5_ader_o <= s_ader(5) when s_ader(5)(c_ADER_DFSR) = '0' else (others => '0');
f6_ader_o <= s_ader(6) when s_ader(6)(c_ADER_DFSR) = '0' else (others => '0');
f7_ader_o <= s_ader(7) when s_ader(7)(c_ADER_DFSR) = '0' else (others => '0');
module_enable_o <= s_reg_bit_reg(4);
vme_sysfail_ena_o <= s_reg_bit_reg(6);
module_reset_o <= s_reg_bit_reg(7);
module_enable_o <= s_reg_bit_reg(c_ENABLE_BIT);
vme_sysfail_ena_o <= s_reg_bit_reg(c_SYSFAIL_EN_BIT);
module_reset_o <= s_reg_bit_reg(c_RESET_BIT);
-- Handle DFS and FAF
s_faf_ader <= (f0_faf_ader_i, f1_faf_ader_i, f2_faf_ader_i, f3_faf_ader_i,
f4_faf_ader_i, f5_faf_ader_i, f6_faf_ader_i, f7_faf_ader_i);
s_dfs_adem <= (f0_dfs_adem_i, f1_dfs_adem_i, f2_dfs_adem_i, f3_dfs_adem_i,
f4_dfs_adem_i, f5_dfs_adem_i, f6_dfs_adem_i, f7_dfs_adem_i);
process (s_reg_ader, s_faf_ader, s_dfs_adem)
process (s_reg_ader, faf_ader_i, dfs_adem_i)
variable v_ader_b0 : std_logic_vector(7 downto 0);
begin
for i in 0 to 7 loop
if (c_ADEM(i-1)(c_ADEM_EFM) = '1' and c_ADEM(i-1)(c_ADEM_FAF) = '1') or
(c_ADEM(i-1)(c_ADEM_EFM) = '0' and c_ADEM(i)(c_ADEM_FAF) = '1')
-- When FAF function or upper bits of previous FAF function, readback
-- and output ADER given at the FAF inputs.
if (g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_FAF) = '1') or
(g_ADEM(i-1)(c_ADEM_EFM) = '0' and g_ADEM( i )(c_ADEM_FAF) = '1')
then
s_ader(i) <= faf_ader_i(i);
ader_o(i) <= faf_ader_i(i);
-- When upper bits of previous DFS function and DFSR enabled, readback
-- the ADEM value and output zero.
elsif g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_DFS) = '1' and
s_reg_ader(i-1)(c_ADER_DFSR) = '1'
then
s_ader(i) <= dfs_adem_i(i);
ader_o(i) <= (others => '0');
-- When a DFS function and DFSR enabled, readback the ADEM and output
-- zero.
elsif g_ADEM(i-1)(c_ADEM_EFM) = '0' and g_ADEM(i)(c_ADEM_DFS) = '1' and
s_reg_ader(i)(c_ADER_DFSR) = '1'
then
s_ader(i) <= s_faf_ader(i);
elsif (c_ADEM(i-1)(c_ADEM_EFM) = '1' and c_ADEM(i-1)(c_ADEM_DFS) = '1' and s_reg_ader(i-1)(c_ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i);
elsif (c_ADEM(i-1)(c_ADEM_EFM) = '0' and c_ADEM(i)(c_ADEM_DFS) = '1' and s_reg_ader(i)(c_ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i)(31 downto 8) & s_reg_ader(i)(7 downto 0);
v_ader_b0 := (c_ADER_DFSR => s_reg_ader(i)(c_ADER_DFSR),
others => '0');
s_ader(i) <= dfs_adem_i(i)(c_ADEM_M) & v_ader_b0;
ader_o(i) <= (others => '0');
-- In all other cases, readback and output the ADER register value.
else
s_ader(i) <= s_reg_ader(i);
ader_o(i) <= s_reg_ader(i);
end if;
end loop;
end process;
-- Read
process (clk_i)
variable v_addr : unsigned(6 downto 2);
variable v_index : integer;
variable v_byte : integer;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_csr_data <= x"ff";
s_csr_data <= c_UNUSED;
else
case s_addr is
when c_ADDR_BAR(18 downto 2) => s_csr_data <= s_reg_bar;
when c_ADDR_BIT_SET_REG(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_ADDR_BIT_CLR_REG(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_ADDR_CRAM_OWNER(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_ADDR_USR_SET_REG(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_ADDR_USR_CLR_REG(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_ADDR_F7_ADER_0(18 downto 2) => s_csr_data <= s_ader(7)( 7 downto 0);
when c_ADDR_F7_ADER_1(18 downto 2) => s_csr_data <= s_ader(7)(15 downto 8);
when c_ADDR_F7_ADER_2(18 downto 2) => s_csr_data <= s_ader(7)(23 downto 16);
when c_ADDR_F7_ADER_3(18 downto 2) => s_csr_data <= s_ader(7)(31 downto 24);
when c_ADDR_F6_ADER_0(18 downto 2) => s_csr_data <= s_ader(6)( 7 downto 0);
when c_ADDR_F6_ADER_1(18 downto 2) => s_csr_data <= s_ader(6)(15 downto 8);
when c_ADDR_F6_ADER_2(18 downto 2) => s_csr_data <= s_ader(6)(23 downto 16);
when c_ADDR_F6_ADER_3(18 downto 2) => s_csr_data <= s_ader(6)(31 downto 24);
when c_ADDR_F5_ADER_0(18 downto 2) => s_csr_data <= s_ader(5)( 7 downto 0);
when c_ADDR_F5_ADER_1(18 downto 2) => s_csr_data <= s_ader(5)(15 downto 8);
when c_ADDR_F5_ADER_2(18 downto 2) => s_csr_data <= s_ader(5)(23 downto 16);
when c_ADDR_F5_ADER_3(18 downto 2) => s_csr_data <= s_ader(5)(31 downto 24);
when c_ADDR_F4_ADER_0(18 downto 2) => s_csr_data <= s_ader(4)( 7 downto 0);
when c_ADDR_F4_ADER_1(18 downto 2) => s_csr_data <= s_ader(4)(15 downto 8);
when c_ADDR_F4_ADER_2(18 downto 2) => s_csr_data <= s_ader(4)(23 downto 16);
when c_ADDR_F4_ADER_3(18 downto 2) => s_csr_data <= s_ader(4)(31 downto 24);
when c_ADDR_F3_ADER_0(18 downto 2) => s_csr_data <= s_ader(3)( 7 downto 0);
when c_ADDR_F3_ADER_1(18 downto 2) => s_csr_data <= s_ader(3)(15 downto 8);
when c_ADDR_F3_ADER_2(18 downto 2) => s_csr_data <= s_ader(3)(23 downto 16);
when c_ADDR_F3_ADER_3(18 downto 2) => s_csr_data <= s_ader(3)(31 downto 24);
when c_ADDR_F2_ADER_0(18 downto 2) => s_csr_data <= s_ader(2)( 7 downto 0);
when c_ADDR_F2_ADER_1(18 downto 2) => s_csr_data <= s_ader(2)(15 downto 8);
when c_ADDR_F2_ADER_2(18 downto 2) => s_csr_data <= s_ader(2)(23 downto 16);
when c_ADDR_F2_ADER_3(18 downto 2) => s_csr_data <= s_ader(2)(31 downto 24);
when c_ADDR_F1_ADER_0(18 downto 2) => s_csr_data <= s_ader(1)( 7 downto 0);
when c_ADDR_F1_ADER_1(18 downto 2) => s_csr_data <= s_ader(1)(15 downto 8);
when c_ADDR_F1_ADER_2(18 downto 2) => s_csr_data <= s_ader(1)(23 downto 16);
when c_ADDR_F1_ADER_3(18 downto 2) => s_csr_data <= s_ader(1)(31 downto 24);
when c_ADDR_F0_ADER_0(18 downto 2) => s_csr_data <= s_ader(0)( 7 downto 0);
when c_ADDR_F0_ADER_1(18 downto 2) => s_csr_data <= s_ader(0)(15 downto 8);
when c_ADDR_F0_ADER_2(18 downto 2) => s_csr_data <= s_ader(0)(23 downto 16);
when c_ADDR_F0_ADER_3(18 downto 2) => s_csr_data <= s_ader(0)(31 downto 24);
when others => s_csr_data <= x"ff";
case to_integer(s_addr) is
when c_BAR_REG =>
s_csr_data <= s_reg_bar;
when c_BIT_SET_REG =>
s_csr_data <= s_reg_bit_reg;
when c_BIT_CLR_REG =>
s_csr_data <= s_reg_bit_reg;
when c_CRAM_OWNER_REG =>
s_csr_data <= s_reg_cram_owner;
when c_USR_SET_REG =>
s_csr_data <= s_reg_usr_bit_reg;
when c_USR_CLR_REG =>
s_csr_data <= s_reg_usr_bit_reg;
when c_ADER_REG_BEG to c_ADER_REG_END =>
v_addr := s_addr(6 downto 2) - to_unsigned(c_ADER_REG_BEG, 5);
v_index := to_integer(v_addr(6 downto 4));
v_byte := 3-to_integer(v_addr(3 downto 2));
s_csr_data <= s_ader(v_index)(8*v_byte+7 downto 8*v_byte);
when others =>
s_csr_data <= c_UNUSED;
end case;
end if;
end if;
......@@ -482,56 +481,57 @@ begin
------------------------------------------------------------------------------
-- CRAM
------------------------------------------------------------------------------
gen_cram: if f_size(g_BEG_CRAM, g_END_CRAM) > 1 generate
s_cram_access <= '1' when s_addr(18 downto 2) >= unsigned(g_BEG_CRAM(18 downto 2)) and
s_addr(18 downto 2) <= unsigned(g_END_CRAM(18 downto 2))
gen_cram_ena: if c_CRAM_ENA = true generate
s_cram_access <= '1' when s_addr >= c_BEG_CRAM and
s_addr <= c_END_CRAM
else '0';
s_cram_addr <= std_logic_vector(s_addr - unsigned(g_BEG_CRAM(18 downto 2)));
s_cram_we <= we_i and s_cram_access;
s_cram_waddr <= s_addr - c_BEG_CRAM;
s_cram_data <= s_cram(to_integer(s_cram_raddr));
cmp_cram: VME_CRAM
generic map (
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM
)
port map (
clk_i => clk_i,
we_i => s_cram_we,
addr_i => s_cram_addr,
data_i => data_i,
data_o => s_cram_data
);
process (clk_i) begin
if rising_edge(clk_i) then
if s_cram_we = '1' then
s_cram(to_integer(s_cram_waddr)) <= data_i;
end if;
s_cram_raddr <= s_cram_waddr;
end if;
end process;
end generate;
gen_no_cram: if f_size(g_BEG_CRAM, g_END_CRAM) <= 1 generate
gen_cram_dis: if c_CRAM_ENA = false generate
s_cram_access <= '0';
s_cram_addr <= (others => '0');
s_cram_raddr <= (others => '0');
s_cram_waddr <= (others => '0');
s_cram_data <= x"00";
end generate;
------------------------------------------------------------------------------
-- User CR/CSR
-- User CR
------------------------------------------------------------------------------
gen_user_cr: if f_size(g_BEG_USER_CR, g_END_USER_CR) > 1 generate
s_user_cr_access <= '1' when s_addr >= unsigned(g_BEG_USER_CR(18 downto 2)) and
s_addr <= unsigned(g_END_USER_CR(18 downto 2))
gen_user_cr_ena: if c_USER_CR_ENA = true generate
s_user_cr_access <= '1' when s_addr >= c_BEG_USER_CR and
s_addr <= c_END_USER_CR
else '0';
user_cr_addr_o <= std_logic_vector(s_addr - unsigned(g_BEG_USER_CR(18 downto 2)));
user_cr_addr_o <= std_logic_vector(s_addr - c_BEG_USER_CR);
end generate;
gen_no_user_cr: if f_size(g_BEG_USER_CR, g_END_USER_CR) <= 1 generate
gen_user_cr_dis: if c_USER_CR_ENA = false generate
s_user_cr_access <= '0';
user_cr_addr_o <= (others => '0');
end generate;
gen_user_csr: if f_size(g_BEG_USER_CSR, g_END_USER_CSR) > 1 generate
s_user_csr_access <= '1' when s_addr >= unsigned(g_BEG_USER_CSR(18 downto 2)) and
s_addr <= unsigned(g_END_USER_CSR(18 downto 2))
------------------------------------------------------------------------------
-- User CSR
------------------------------------------------------------------------------
gen_user_csr_ena: if c_USER_CSR_ENA = true generate
s_user_csr_access <= '1' when s_addr >= c_BEG_USER_CSR and
s_addr <= c_END_USER_CSR
else '0';
user_csr_addr_o <= std_logic_vector(s_addr - unsigned(g_BEG_USER_CSR(18 downto 2)));
user_csr_addr_o <= std_logic_vector(s_addr - c_BEG_USER_CSR);
end generate;
gen_no_user_csr: if f_size(g_BEG_USER_CSR, g_END_USER_CSR) <= 1 generate
gen_user_csr_dis: if c_USER_CSR_ENA = false generate
s_user_csr_access <= '0';
user_csr_addr_o <= (others => '0');
end generate;
......@@ -540,7 +540,7 @@ begin
user_csr_we_o <= we_i and s_user_csr_access;
------------------------------------------------------------------------------
-- Read Multiplexer
-- Read multiplexer
------------------------------------------------------------------------------
process (
s_cr_access, s_cr_data,
......@@ -560,7 +560,7 @@ begin
elsif s_user_csr_access = '1' then
data_o <= user_csr_data_i;
else
data_o <= x"ff";
data_o <= c_UNUSED;
end if;
end process;
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 72eff0ad
......@@ -4,167 +4,13 @@
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Funct_Match (VME_Funct_Match.vhd)
-- unit name: VME_Funct_Match (VME_Funct_Match.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
--
-- This component compares the Address with the ADER using the mask bits and
-- if the base address match it asserts the corresponding bit in the
-- FunctMatch vector and it latches the base address that will be subtracted
-- to the Address before accessing the WB bus.
--
-- FunctMatch /= 0 is necessary but not sufficient to select one function and
-- to access the board, indeed also the AM has to be checked (VME_AM_Match.vhd
-- component).
--
-- For better understanding how this component works here is one example:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master writes the ADERi = 0xc0000024
-- ADEMi = 0xffffff04 --> DFS = '1' --> all the mask bits are '1'!!
-- The Master wants to access the location 0x08: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
--
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00000 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- Now with the same ADEMi the master accesses with A16 mode:
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master writes the ADERi = 0x0000c0a4
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[15:8] /= 0
--
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0x0000c0 0x0000c0
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- DFS = '1' --> 1 function --> multiple access modes
-- The Master accesses with different modes only changing the ADER registers
-- if the DFS bit is asserted but:
-- It is easy to see that if DFS = '1' we can only address 256 bytes, indeed
-- eg:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
--
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00040 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- The Master can't access!!
-- Without DFS asserted:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- ADEMi = 0xff000000 --> DFS = '0'
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEM[31:8] /= 0
--
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00000 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- The Master can access!
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master writes the ADERi = 0x0000c0a4
-- ADEMi = 0xff000000 --> DFS = '0' -- The Master can't change the CR space!!
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected:
-- ADEM[15:8] = 0 --> FunctMatch(i) <= '0'
-- The Master can't access! this mask is not compatible with A16
--
-- DFS = '0' --> 1 function --> only the access modes with the same
-- address width !!
-- Is it possible initialize all the ADER to 0 ?
-- Yes, it is. Indeed now suppose that we are in this situation:
-- ADERi = 0x00000000
-- ADEMi = 0x0000ff00 --> DFS = '0'
-- A VME Master takes the ownership of the VMEbus for accessing another board:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master wants to access the location 0x0008: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
--
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0x000000 0x000000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- FunctMatch(i) is asserted but our Slave will not be the responding Slave,
-- indeed the AmMatch(i) is zero becouse the Master is accessing with A32_S
-- and if DFS is 0 the AMCAPi register has only the A16 or A16_SUP bits
-- asserted!
-- If DFS is '1' AmMatch(i) is zero becouse ADER[7:2] is 0
-- (see VME_Am_Match.vhd) and also FunctMatch(i) is 0 because ADEMi should has
-- all the mask bits '1'.
--
-- An example about A64 access mode:
-- base address = 0xc0
-- access mode: A64_S --> AM = 0x01
-- ADEM(i) = 0x00000001 --> EFM = '1' and DFS = '0'
-- ADEM(i+1) = 0xff000000
-- ADEM64(i) = ADEM(i+1) & ADEM(i)
-- AMCAP(i) = "0000000000000000000000000000000000000000000000000000000000000010";
-- AMCAP(i+1) = (others => '0')
-- ADER(i) = 0x00000004
-- ADER(i+1) = 0xc0000000
-- ADER64(i) = ADER(i+1) & ADER(i)
-- s_isprev_func64(i+1) --> '1' --> don't check if the function i + 1 is
-- selected because the next ADER and ADEM are used to decode the function i.
-- The Master accesses the location 0x0008: Address= 0xc000000000000008
-- Check if the ADEM64i is compatible with the AM selected:
-- ADEM64(i)[63:10] /= 0
--
-- Address[63:10] and ADEM64(i)[63:10] ADER64(i)[63:10] and ADEM64(i)[63:10]
-- | |
-- 0xc0000000000000 0xc0000000000000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- For the 2e modes it is the same, it changes only the ADER(i)'s XAM bit that
-- must be '1'.
-- dependencies:
--
--------------------------------------------------------------------------------
......@@ -191,148 +37,368 @@ use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_Funct_Match is
generic (
g_ADEM : t_adem_array(-1 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7)
);
port (
clk_i : in std_logic;
reset : in std_logic;
decode : in std_logic;
mainFSMreset : in std_logic;
Addr : in std_logic_vector(63 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
FunctMatch : out std_logic_vector(7 downto 0);
DFS_o : out std_logic_vector(7 downto 0);
Nx_Base_Addr : out std_logic_vector(63 downto 0)
clk_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(63 downto 0);
addr_o : out std_logic_vector(63 downto 0);
decode_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0);
xam_i : in std_logic_vector( 7 downto 0);
ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7);
sel_o : out std_logic;
function_o : out std_logic_vector( 3 downto 0)
);
end VME_Funct_Match;
architecture Behavioral of VME_Funct_Match is
architecture rtl of VME_Funct_Match is
signal s_FUNC_ADER,
s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_ADER_64,
s_FUNC_ADEM_64 : t_FUNC_64b_array;
signal s_isprev_func64 : std_logic_vector(7 downto 0);
signal s_locAddr : unsigned(63 downto 0);
type t_addr_array is array (0 to 7) of std_logic_vector(63 downto 0);
begin
signal s_ader : t_addr_array;
signal s_adem : t_addr_array;
-- AM matches ADER AM bits for each function
signal s_am_match : std_logic_vector( 7 downto 0);
-- AM/XAM in AMCAP/XAMCAP for each function
signal s_am_valid : std_logic_vector( 8 downto 0);
signal s_xam_valid : std_logic_vector( 7 downto 0);
-- Function index and ADEM from priority encoder
signal s_function_sel : std_logic_vector( 7 downto 0);
signal s_adem_sel : std_logic_vector(63 downto 0);
-- Selected function
signal s_function : std_logic_vector( 7 downto 0);
signal s_function_ena : std_logic_vector( 7 downto 0);
s_locAddr <= unsigned(Addr);
------------------------------------------------------------------------------
-- Generate AM lookup table
------------------------------------------------------------------------------
-- There are 64 positions in the LUT corresponding to each AM. Each position
-- is a vector whose bit N indicate whether function N accepts this AM.
-- For example if s_am_lut(9) = "00001010", this means that functions 1 & 3
-- accept AM=9. The lookup table has an extra bit (8) which is set only for
-- the 2eVME AMs (0x20 & 0x21) to indicate that these are valid in XAM mode.
type t_am_lut is array (0 to 63) of std_logic_vector(8 downto 0);
p_functMatch : process (clk_i)
function f_gen_am_lut return t_am_lut is
variable lut : t_am_lut := (others => "000000000");
begin
if rising_edge(clk_i) then
if mainFSMreset = '1' or reset = '1' then
FunctMatch <= (others => '0');
Nx_Base_Addr <= (others => '0');
elsif decode = '1' then
for i in FunctMatch'range loop
case AddrWidth is
when "11" =>
if (s_FUNC_ADEM(i)(0) = '1') and (s_isprev_func64(i) = '0') and
(s_FUNC_ADEM_64(i)(63 downto 10) /= 0)
then
if (s_FUNC_ADER_64(i)(63 downto 10) and s_FUNC_ADEM_64(i)(63 downto 10)) =
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10))
then
FunctMatch(i) <= '1';
Nx_Base_Addr(63 downto 10) <= std_logic_vector(s_FUNC_ADER_64(i)(63 downto 10));
Nx_Base_Addr(9 downto 0) <= (others => '0');
end if;
end if;
when "10" =>
if (s_FUNC_ADEM(i)(31 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(31 downto 8) and s_FUNC_ADEM(i)(31 downto 8)) =
((s_locAddr(31 downto 8)) and s_FUNC_ADEM(i)(31 downto 8))
then
FunctMatch(i) <= '1';
Nx_Base_Addr(31 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(31 downto 8));
Nx_Base_Addr(63 downto 32) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
when "01" =>
if (s_FUNC_ADEM(i)(23 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(23 downto 8) and s_FUNC_ADEM(i)(23 downto 8)) =
((s_locAddr(23 downto 8)) and s_FUNC_ADEM(i)(23 downto 8))
then
FunctMatch(i) <= '1';
Nx_Base_Addr(23 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(23 downto 8));
Nx_Base_Addr(63 downto 24) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
when "00" =>
if (s_FUNC_ADEM(i)(15 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(15 downto 8) and s_FUNC_ADEM(i)(15 downto 8)) =
((s_locAddr(15 downto 8)) and s_FUNC_ADEM(i)(15 downto 8))
then
FunctMatch(i) <= '1';
Nx_Base_Addr(15 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(15 downto 8));
Nx_Base_Addr(63 downto 16) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
when others =>
end case;
for i in 0 to 63 loop
for j in 0 to 7 loop
lut(i)(j) := g_AMCAP(j)(i);
end loop;
end loop;
lut(to_integer(unsigned(c_AM_2EVME_6U)))(8) := '1';
lut(to_integer(unsigned(c_AM_2EVME_3U)))(8) := '1';
return lut;
end function;
signal s_am_lut : t_am_lut := f_gen_am_lut;
------------------------------------------------------------------------------
-- Generate XAM lookup table
------------------------------------------------------------------------------
-- Same purpose as the AM lookup table, with 256 positions for each XAM.
type t_xam_lut is array (0 to 255) of std_logic_vector(7 downto 0);
function f_gen_xam_lut return t_xam_lut is
variable lut : t_xam_lut;
begin
for i in 0 to 255 loop
for j in 0 to 7 loop
lut(i)(j) := g_XAMCAP(j)(i);
end loop;
end loop;
return lut;
end function;
signal s_xam_lut : t_xam_lut := f_gen_xam_lut;
------------------------------------------------------------------------------
-- Generate XAM enabled flag
------------------------------------------------------------------------------
-- c_XAM_ENA is true when any XAMCAP > 0 to conditionally enable the
-- generation of the XAM lookup table.
function f_xam_ena return boolean is
begin
for i in 0 to 7 loop
if unsigned(g_XAMCAP(i)) > 0 then
return true;
end if;
end loop;
return false;
end function;
constant c_XAM_ENA : boolean := f_xam_ena;
------------------------------------------------------------------------------
-- Generate function enabled vector
------------------------------------------------------------------------------
-- c_ENABLED is true when a function's AMCAP > 0 and the previous
-- function does not have the EFM bit set.
function f_function_ena return std_logic_vector is
variable ena : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in 0 to 7 loop
if unsigned(g_AMCAP(i)) > 0 and g_ADEM(i-1)(c_ADEM_EFM) = '0' then
ena(i) := '1';
end if;
end loop;
return ena;
end function;
constant c_ENABLED : std_logic_vector(7 downto 0) := f_function_ena;
------------------------------------------------------------------------------
-- Generate function EFM/EFD enabled vector
------------------------------------------------------------------------------
function f_efm_efd (v : integer) return std_logic_vector is
variable e : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in 0 to 6 loop
e(i) := g_ADEM(i)(v);
end loop;
return e;
end function;
constant c_EFM : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFM);
constant c_EFD : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFD);
constant c_EFD_ENA : boolean := unsigned(c_EFD) > 0;
------------------------------------------------------------------------------
-- Generate EFD lookup table
------------------------------------------------------------------------------
type t_efd_lut is array (0 to 7) of std_logic_vector(7 downto 0);
function f_gen_efd_lut return t_efd_lut is
variable lut : t_efd_lut;
begin
for i in 0 to 7 loop
if g_ADEM(i-1)(c_ADEM_EFD) = '1' then
for j in i-1 downto 0 loop
if g_ADEM(j-1)(c_ADEM_EFD) = '0' then
lut(i) := std_logic_vector(to_unsigned(j, 8));
exit;
end if;
end loop;
else
lut(i) := std_logic_vector(to_unsigned(i, 8));
end if;
end loop;
return lut;
end function;
constant c_EFD_LUT : t_efd_lut := f_gen_efd_lut;
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
-- AM lookup table
------------------------------------------------------------------------------
process (clk_i) begin
if rising_edge(clk_i) then
s_am_valid <= s_am_lut(to_integer(unsigned(am_i)));
end if;
end process;
------------------------------------------------------------------------------
-- XAM lookup table
------------------------------------------------------------------------------
gen_xam_ena : if c_XAM_ENA = true generate
process (clk_i) begin
if rising_edge(clk_i) then
s_xam_valid <= s_xam_lut(to_integer(unsigned(xam_i)));
end if;
end process;
end generate;
gen_xam_dis : if c_XAM_ENA = false generate
s_xam_valid <= x"00";
end generate;
------------------------------------------------------------------------------
-- Function match
------------------------------------------------------------------------------
gen_match_loop : for i in 0 to 7 generate
gen_ena_function: if c_ENABLED(i) = '1' generate
-- Create 64-bit ADEM/ADER based on EFM and DFS setting
gen_efm_ena: if c_EFM(i) = '1' generate
gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate
s_adem(i) <= dfs_adem_i(i+1) & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
gen_dfs_dis: if g_ADEM(i)(c_ADEM_DFS) = '0' generate
s_adem(i) <= g_ADEM(i+1) & g_ADEM(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
s_ader(i)(63 downto 32) <= ader_i(i+1);
end generate;
gen_efm_dis: if c_EFM(i) = '0' generate
gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate
s_adem(i) <= x"ffff_ffff" & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
gen_dfs_dis: if g_ADEM(i)(c_ADEM_DFS) = '0' generate
s_adem(i) <= x"ffff_ffff" & g_ADEM(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
s_ader(i)(63 downto 32) <= x"0000_0000";
end generate;
process (ader_i(i), am_i, xam_i) begin
if ader_i(i)(c_ADER_XAM_MODE) then
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_XAM) & c_ADER_C_XAM_PAD;
if ader_i(i)(c_ADER_XAM) = xam_i then
s_am_match(i) <= '1';
else
s_am_match(i) <= '1';
end if;
else
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_AM) & c_ADER_C_AM_PAD;
if ader_i(i)(c_ADER_AM) = am_i then
s_am_match(i) <= '1';
else
s_am_match(i) <= '1';
end if;
end if;
end process;
s_function(i) <= '1' when (addr_i and s_adem(i)) = s_ader(i) and
s_am_match(i) = '1'
else '0';
end generate;
gen_dis_function: if c_ENABLED(i) = '0' generate
s_adem(i) <= (others => '0');
s_ader(i) <= (others => '0');
s_am_match(i) <= '0';
s_function(i) <= '0';
end generate;
end generate;
------------------------------------------------------------------------------
-- Function priority encoder
------------------------------------------------------------------------------
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_function_sel <= (others => '0');
s_adem_sel <= (others => '0');
else
if s_function(0) = '1' then
s_function_sel <= "00000001";
s_adem_sel <= s_adem(0);
elsif s_function(1) = '1' then
s_function_sel <= "00000010";
s_adem_sel <= s_adem(1);
elsif s_function(2) = '1' then
s_function_sel <= "00000100";
s_adem_sel <= s_adem(2);
elsif s_function(3) = '1' then
s_function_sel <= "00001000";
s_adem_sel <= s_adem(3);
elsif s_function(4) = '1' then
s_function_sel <= "00010000";
s_adem_sel <= s_adem(4);
elsif s_function(5) = '1' then
s_function_sel <= "00100000";
s_adem_sel <= s_adem(5);
elsif s_function(6) = '1' then
s_function_sel <= "01000000";
s_adem_sel <= s_adem(6);
elsif s_function(7) = '1' then
s_function_sel <= "10000000";
s_adem_sel <= s_adem(7);
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Check of AM/XAM against AMCAP/XAMCAP
------------------------------------------------------------------------------
process (s_ader, s_am_valid, s_xam_valid, s_function_sel) begin
for i in 0 to 7 loop
if s_ader(i)(c_ADER_XAM_MODE) = '1' then
s_function_ena(i) <= s_function_sel(i) and s_am_valid(i) and
s_xam_valid(i) and s_am_valid(8);
else
s_function_ena(i) <= s_function_sel(i) and s_am_valid(i);
end if;
end loop;
end process;
------------------------------------------------------------------------------
-- Address output latch
------------------------------------------------------------------------------
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
addr_o <= (others => '0');
else
if decode_i then
addr_o <= addr_i and not s_adem_sel;
end if;
end if;
end if;
end process;
s_FUNC_ADER(0) <= unsigned(Ader0);
s_FUNC_ADER(1) <= unsigned(Ader1);
s_FUNC_ADER(2) <= unsigned(Ader2);
s_FUNC_ADER(3) <= unsigned(Ader3);
s_FUNC_ADER(4) <= unsigned(Ader4);
s_FUNC_ADER(5) <= unsigned(Ader5);
s_FUNC_ADER(6) <= unsigned(Ader6);
s_FUNC_ADER(7) <= unsigned(Ader7);
s_FUNC_ADEM(0) <= unsigned(Adem0);
s_FUNC_ADEM(1) <= unsigned(Adem1);
s_FUNC_ADEM(2) <= unsigned(Adem2);
s_FUNC_ADEM(3) <= unsigned(Adem3);
s_FUNC_ADEM(4) <= unsigned(Adem4);
s_FUNC_ADEM(5) <= unsigned(Adem5);
s_FUNC_ADEM(6) <= unsigned(Adem6);
s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(c_ADEM_DFS);
end generate GDFS;
GADER_64 : for i in 0 to 6 generate
s_FUNC_ADER_64(i) <= s_FUNC_ADER(i+1)&s_FUNC_ADER(i);
end generate GADER_64;
s_FUNC_ADER_64(7) <= (others => '0');
GADEM_64 : for i in 0 to 6 generate
s_FUNC_ADEM_64(i) <= s_FUNC_ADEM(i+1)&s_FUNC_ADEM(i);
s_isprev_func64(i+1) <= s_FUNC_ADEM(i)(0);
end generate GADEM_64;
s_isprev_func64(0) <= '0';
s_FUNC_ADEM_64(7) <= (others => '0');
end Behavioral;
------------------------------------------------------------------------------
-- EFD decoder and output latch
------------------------------------------------------------------------------
gen_efd_ena: if c_EFD_ENA = true generate
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
function_o <= (others => '0');
else
if decode_i then
case s_function_ena is
when "00000001" => function_o <= c_EFD_LUT(0);
when "00000010" => function_o <= c_EFD_LUT(1);
when "00000100" => function_o <= c_EFD_LUT(2);
when "00001000" => function_o <= c_EFD_LUT(3);
when "00010000" => function_o <= c_EFD_LUT(4);
when "00100000" => function_o <= c_EFD_LUT(5);
when "01000000" => function_o <= c_EFD_LUT(6);
when "10000000" => function_o <= c_EFD_LUT(7);
when others => function_o <= (others => '0');
end case;
end if;
end if;
end if;
end process;
end generate;
gen_efd_dis: if c_EFD_ENA = false generate
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
function_o <= (others => '0');
else
if decode_i then
function_o <= s_function_ena;
end if;
end if;
end if;
end process;
end generate;
end rtl;
hdl/vme64x-core/rtl/VME_User_CSR.vhd
View file @ 72eff0ad
......@@ -91,43 +91,55 @@ end VME_User_CSR;
architecture rtl of VME_User_CSR is
signal s_addr : unsigned(18 downto 2);
signal s_irq_vector : std_logic_vector(7 downto 0);
signal s_irq_level : std_logic_vector(7 downto 0);
signal s_endian : std_logic_vector(7 downto 0);
signal s_wb32bits : std_logic_vector(7 downto 0);
signal s_reg_irq_vector : std_logic_vector(7 downto 0);
signal s_reg_irq_level : std_logic_vector(7 downto 0);
signal s_reg_endian : std_logic_vector(7 downto 0);
signal s_reg_wb32bits : std_logic_vector(7 downto 0);
-- Value for unused memory locations
constant c_UNUSED : std_logic_vector(7 downto 0) := x"ff";
begin
-- Addresses
constant c_IRQ_VECTOR : integer := 16#0002f#/4;
constant c_IRQ_LEVEL : integer := 16#0002b#/4;
constant c_ENDIAN : integer := 16#00023#/4;
constant c_TIME0_NS : integer := 16#0001f#/4;
constant c_TIME1_NS : integer := 16#0001b#/4;
constant c_TIME2_NS : integer := 16#00017#/4;
constant c_TIME3_NS : integer := 16#00013#/4;
constant c_TIME4_NS : integer := 16#0000f#/4;
constant c_BYTES0 : integer := 16#0000b#/4;
constant c_BYTES1 : integer := 16#00007#/4;
constant c_WB32BITS : integer := 16#00003#/4;
s_addr <= unsigned(addr_i);
begin
s_reg_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
s_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
-- Write
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_reg_irq_vector <= x"00";
s_reg_irq_level <= x"00";
s_reg_endian <= x"00";
s_irq_vector <= x"00";
s_irq_level <= x"00";
s_endian <= x"00";
else
if we_i = '1' then
case s_addr is
when c_ADDR_IRQ_VECTOR(18 downto 2) => s_reg_irq_vector <= data_i;
when c_ADDR_IRQ_LEVEL(18 downto 2) => s_reg_irq_level <= data_i;
when c_ADDR_ENDIAN(18 downto 2) => s_reg_endian <= data_i;
when others => null;
case to_integer(unsigned(addr_i)) is
when c_IRQ_VECTOR => s_irq_vector <= data_i;
when c_IRQ_LEVEL => s_irq_level <= data_i;
when c_ENDIAN => s_endian <= data_i;
when others => null;
end case;
end if;
end if;
end if;
end process;
irq_vector_o <= s_reg_irq_vector;
irq_level_o <= s_reg_irq_level;
endian_o <= s_reg_endian(2 downto 0);
irq_vector_o <= s_irq_vector;
irq_level_o <= s_irq_level;
endian_o <= s_endian(2 downto 0);
-- Read
process (clk_i)
......@@ -136,19 +148,19 @@ begin
if rst_n_i = '0' then
data_o <= x"00";
else
case s_addr is
when c_ADDR_IRQ_VECTOR(18 downto 2) => data_o <= s_reg_irq_vector;
when c_ADDR_IRQ_LEVEL(18 downto 2) => data_o <= s_reg_irq_level;
when c_ADDR_ENDIAN(18 downto 2) => data_o <= s_reg_endian;
when c_ADDR_TIME0_NS(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_ADDR_TIME1_NS(18 downto 2) => data_o <= time_i(15 downto 8);
when c_ADDR_TIME2_NS(18 downto 2) => data_o <= time_i(23 downto 16);
when c_ADDR_TIME3_NS(18 downto 2) => data_o <= time_i(31 downto 24);
when c_ADDR_TIME4_NS(18 downto 2) => data_o <= time_i(39 downto 32);
when c_ADDR_BYTES0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_ADDR_BYTES1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_ADDR_WB32BITS(18 downto 2) => data_o <= s_reg_wb32bits;
when others => data_o <= x"ff";
case to_integer(unsigned(addr_i)) is
when c_IRQ_VECTOR => data_o <= s_irq_vector;
when c_IRQ_LEVEL => data_o <= s_irq_level;
when c_ENDIAN => data_o <= s_endian;
when c_TIME0_NS => data_o <= time_i( 7 downto 0);
when c_TIME1_NS => data_o <= time_i(15 downto 8);
when c_TIME2_NS => data_o <= time_i(23 downto 16);
when c_TIME3_NS => data_o <= time_i(31 downto 24);
when c_TIME4_NS => data_o <= time_i(39 downto 32);
when c_BYTES0 => data_o <= bytes_i( 7 downto 0);
when c_BYTES1 => data_o <= bytes_i(15 downto 8);
when c_WB32BITS => data_o <= s_wb32bits;
when others => data_o <= c_UNUSED;
end case;
end if;
end if;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 72eff0ad
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
......@@ -13,23 +14,22 @@
-- This block acts as interface between the VMEbus and the CR/CSR space or
-- WBbus.
--
-- _____________VME_bus________________
-- | |
-- | ______ _______ |
-- | | A D | | | ____|
-- | | C E | | M F | | W |
-- | | C C | | A S | | B |
-- VME | | E O | | I M | | |
-- BUS | | S D | | N | | M |
-- | | S E | | | | A |
-- | |______| |_______| | S |
-- | __________________ | T |
-- | | | | E |
-- | | OTHER DATA & | | R |
-- | | ADDR PROCESS | |____|
-- | | | |
-- | |__________________| |
-- |____________________________________|
-- _________VME_bus__________
-- | __________________ |
-- | | | ___|
-- | | | | |
-- | | MAIN | | W |
-- V | | | | B | W
-- M | | FSM | | | B
-- E | | | | M |
-- | | | | A | B
-- B | |__________________| | S | U
-- U | __________________ | T | S
-- S | | | | E |
-- | | OTHER DATA & | | R |
-- | | ADDR PROCESS | |___|
-- | |__________________| |
-- |__________________________|
--
-- The Access decode component decodes the address to check if the board is
-- the responding Slave. This component is of fundamental importance, indeed
......@@ -71,37 +71,7 @@ entity VME_bus is
generic (
g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer;
g_BEG_USER_CR : std_logic_vector( 23 downto 0);
g_END_USER_CR : std_logic_vector( 23 downto 0);
g_BEG_CRAM : std_logic_vector( 23 downto 0);
g_END_CRAM : std_logic_vector( 23 downto 0);
g_BEG_USER_CSR : std_logic_vector( 23 downto 0);
g_END_USER_CSR : std_logic_vector( 23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0)
g_WB_ADDR_WIDTH : integer
);
port (
clk_i : in std_logic;
......@@ -144,19 +114,20 @@ entity VME_bus is
rty_i : in std_logic;
stall_i : in std_logic;
-- Function decoder
addr_decoder_i : in std_logic_vector(63 downto 0);
addr_decoder_o : out std_logic_vector(63 downto 0);
decode_o : out std_logic;
am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0);
sel_i : in std_logic;
function_i : in std_logic_vector( 7 downto 0);
--CR/CSR space signals:
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
f0_ader_i : in std_logic_vector(31 downto 0);
f1_ader_i : in std_logic_vector(31 downto 0);
f2_ader_i : in std_logic_vector(31 downto 0);
f3_ader_i : in std_logic_vector(31 downto 0);
f4_ader_i : in std_logic_vector(31 downto 0);
f5_ader_i : in std_logic_vector(31 downto 0);
f6_ader_i : in std_logic_vector(31 downto 0);
f7_ader_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
......@@ -188,7 +159,7 @@ architecture RTL of VME_bus is
signal s_locAddrBeforeOffset : unsigned(63 downto 0);
signal s_phase1addr : unsigned(63 downto 0); -- for 2e transfers
signal s_phase2addr : unsigned(63 downto 0); --
--signal s_phase3addr : unsigned(63 downto 0); --
--signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- block transfers|
signal s_DataShift : unsigned(5 downto 0);
-- uncomment if 2e is implemented:
......@@ -202,7 +173,6 @@ architecture RTL of VME_bus is
signal s_LWORDlatched : std_logic; -- Stores LWORD on falling edge of AS
signal s_DSlatched : std_logic_vector(1 downto 0); -- Stores DS
signal s_AMlatched : std_logic_vector(5 downto 0); -- Latch on AS f. edge
signal s_XAM : unsigned(7 downto 0); -- Stores received XAM
-- Type of data transfer (depending on VME_DS_n, VME_LWORD_n and VME_ADDR(1))
signal s_typeOfDataTransfer : t_typeOfDataTransfer;
......@@ -240,8 +210,8 @@ architecture RTL of VME_bus is
--signal s_berr_2 : std_logic; --
-- Access decode signals
signal s_confAccess : std_logic; -- Asserted when CR or CSR is addressed
signal s_cardSel : std_logic; -- Asserted when WB memory is addressed
signal s_conf_sel : std_logic; -- Asserted when CR or CSR is addressed
signal s_card_sel : std_logic; -- Asserted when WB memory is addressed
-- WishBone signals
signal s_sel : unsigned(7 downto 0); -- SEL WB signal
......@@ -256,7 +226,6 @@ architecture RTL of VME_bus is
signal s_prev_VME_AS_n : std_logic;
signal s_is_d64 : std_logic;
signal s_base_addr : unsigned(63 downto 0);
signal s_nx_base_addr : std_logic_vector(63 downto 0);
signal s_VMEdata64In : unsigned(63 downto 0);
signal s_BERR_out : std_logic;
......@@ -379,7 +348,8 @@ begin
A64 when c_AM_A64,
A64_BLT when c_AM_A64_BLT,
A64_MBLT when c_AM_A64_MBLT,
TWOedge when c_AM_TWOEDGE,
TWOedge when c_AM_2EVME_6U,
TWOedge when c_AM_2EVME_3U,
AM_Error when others;
-- Transfer type decoder
......@@ -484,9 +454,9 @@ begin
--if s_addressingType = TWOedge then
---- start 2e transfer
--s_mainFSMstate <= WAIT_FOR_DS_2e;
if s_confAccess = '1' or s_cardSel = '1' then
-- confAccess = '1' it means CR/CSR space addressed
-- s_cardSel = '1' it means WB application addressed
if s_conf_sel = '1' or s_card_sel = '1' then
-- conf_sel = '1' it means CR/CSR space addressed
-- card_sel = '1' it means WB application addressed
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= DECODE_ACCESS;
......@@ -974,9 +944,9 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if s_cardSel = '1' then
if s_card_sel = '1' then
s_locDataOut <= unsigned(s_locDataOutWb);
elsif s_confAccess = '1' then
elsif s_conf_sel = '1' then
s_locDataOut <= resize(unsigned(cr_csr_data_i), s_locDataOut'length);
else
s_locDataOut <= (others => '0');
......@@ -1078,7 +1048,7 @@ begin
port map (
memReq_i => s_memReq,
clk_i => clk_i,
cardSel_i => s_cardSel,
cardSel_i => s_card_sel,
reset_i => s_wbMaster_rst,
BERRcondition_i => s_BERRcondition,
sel_i => std_logic_vector(s_sel),
......@@ -1105,64 +1075,19 @@ begin
we_o <= not s_rw;
------------------------------------------------------------------------------
-- Decoder
-- Function Decoder
------------------------------------------------------------------------------
-- This component check if the board is addressed; if the CR/CSR space is
-- addressed the Confaccess signal is asserted
-- If the Wb memory is addressed the CardSel signal is asserted.
s_XAM <= (others => '0');
Inst_Access_Decode : VME_Access_Decode
port map (
clk_i => clk_i,
reset => rst_i,
mainFSMreset => s_mainFSMreset,
decode => s_decode,
ModuleEnable => module_enable_i,
Addr => std_logic_vector(s_locAddr),
Ader0 => f0_ader_i,
Ader1 => f1_ader_i,
Ader2 => f2_ader_i,
Ader3 => f3_ader_i,
Ader4 => f4_ader_i,
Ader5 => f5_ader_i,
Ader6 => f6_ader_i,
Ader7 => f7_ader_i,
Adem0 => g_F0_ADEM,
Adem1 => g_F1_ADEM,
Adem2 => g_F2_ADEM,
Adem3 => g_F3_ADEM,
Adem4 => g_F4_ADEM,
Adem5 => g_F5_ADEM,
Adem6 => g_F6_ADEM,
Adem7 => g_F7_ADEM,
AmCap0 => g_F0_AMCAP,
AmCap1 => g_F1_AMCAP,
AmCap2 => g_F2_AMCAP,
AmCap3 => g_F3_AMCAP,
AmCap4 => g_F4_AMCAP,
AmCap5 => g_F5_AMCAP,
AmCap6 => g_F6_AMCAP,
AmCap7 => g_F7_AMCAP,
XAmCap0 => g_F0_XAMCAP,
XAmCap1 => g_F1_XAMCAP,
XAmCap2 => g_F2_XAMCAP,
XAmCap3 => g_F3_XAMCAP,
XAmCap4 => g_F4_XAMCAP,
XAmCap5 => g_F5_XAMCAP,
XAmCap6 => g_F6_XAMCAP,
XAmCap7 => g_F7_XAMCAP,
Am => s_AMlatched,
XAm => std_logic_vector(s_XAM),
BAR_i => bar_i,
AddrWidth => s_addrWidth,
Funct_Sel => open,
Base_Addr => s_nx_base_addr,
Confaccess => s_confAccess,
CardSel => s_cardSel
);
s_base_addr <= unsigned(s_nx_base_addr);
s_base_addr <= unsigned(addr_decoder_i);
addr_decoder_o <= std_logic_vector(s_locAddr);
decode_o <= s_decode;
am_o <= s_amlatched;
xam_o <= (others => '0');
s_card_sel <= sel_i;
-- Decode accesses to CR/CSR
s_conf_sel <= '1' when s_locAddr(23 downto 19) = unsigned(bar_i) and
s_amlatched = c_AM_CR_CSR
else '0';
------------------------------------------------------------------------------
-- Acknowledge
......@@ -1182,7 +1107,7 @@ begin
if rst_i = '1' then
s_memAckCSR <= '0';
else
if s_memReq = '1' and s_confAccess = '1' then
if s_memReq = '1' and s_conf_sel = '1' then
s_memAckCSR <= '1';
else
s_memAckCSR <= '0';
......@@ -1197,9 +1122,9 @@ begin
cr_csr_data_o <= std_logic_vector(s_locDataIn(7 downto 0));
cr_csr_addr_o <= std_logic_vector(s_locAddr(18 downto 2));
cr_csr_we_o <= '1' when s_memReq = '1' and
s_confAccess = '1' and
s_RW = '0'
cr_csr_we_o <= '1' when s_memReq = '1' and
s_conf_sel = '1' and
s_RW = '0'
else '0';
------------------------------------------------------------------------------
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 72eff0ad
......@@ -52,11 +52,19 @@ package vme64x_pack is
constant c_PROGRAM_ID : std_logic_vector( 7 downto 0) := x"5a";
-- Bits in ADEM/ADER registers
subtype c_ADEM_M is integer range 31 downto 8;
constant c_ADEM_M_PAD : std_logic_vector(7 downto 0) := (others => '0');
constant c_ADEM_FAF : integer := 3;
constant c_ADEM_DFS : integer := 2;
constant c_ADEM_EFD : integer := 1;
constant c_ADEM_EFM : integer := 0;
subtype c_ADER_C_XAM is integer range 31 downto 10;
constant c_ADER_C_XAM_PAD : std_logic_vector(9 downto 0) := (others => '0');
subtype c_ADER_C_AM is integer range 31 downto 8;
constant c_ADER_C_AM_PAD : std_logic_vector(7 downto 0) := (others => '0');
subtype c_ADER_AM is integer range 7 downto 2;
subtype c_ADER_XAM is integer range 9 downto 2;
constant c_ADER_DFSR : integer := 1;
constant c_ADER_XAM_MODE : integer := 0;
......@@ -86,84 +94,25 @@ package vme64x_pack is
constant c_AM_A64_BLT : std_logic_vector(5 downto 0) := "000011"; -- 0x03
constant c_AM_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; -- 0x00
constant c_AM_A64_LCK : std_logic_vector(5 downto 0) := "000100"; -- 0x04
constant c_AM_TWOEDGE : std_logic_vector(5 downto 0) := "100000"; -- 0x20
constant c_AM_2EVME_6U : std_logic_vector(5 downto 0) := "100000"; -- 0x20
constant c_AM_2EVME_3U : std_logic_vector(5 downto 0) := "100001"; -- 0x21
constant c_AM_A32_2EVME : std_logic_vector(7 downto 0) := "00000001"; -- 0x01
constant c_AM_A64_2EVME : std_logic_vector(7 downto 0) := "00000010"; -- 0x02
constant c_AM_A32_2ESST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11
constant c_AM_A64_2ESST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12
-- Defined CR area
constant c_BEG_CR : unsigned(19 downto 0) := x"00000";
constant c_END_CR : unsigned(19 downto 0) := x"00FFF";
-- Defined CSR area
-- NOTE: by the standard, the defined CSR area is from 7FC00..7FFFF and the
-- area from 7FC00..7FF5F is reserved. However the previous version of
-- this core placed some user defined registers from 7FF30..7FF5F.
-- Therefore, to allow compatibility with that version, the reserved
-- area is not decoded as part of the defined CSR. However, it is not
-- advisable to place any registers in this area in new designs.
constant c_BEG_CSR : unsigned(19 downto 0) := x"7FF60";
constant c_END_CSR : unsigned(19 downto 0) := x"7FFFF";
-- Defined CSR addresses
constant c_ADDR_BAR : unsigned(19 downto 0) := x"7FFFF";
constant c_ADDR_BIT_SET_REG : unsigned(19 downto 0) := x"7FFFB";
constant c_ADDR_BIT_CLR_REG : unsigned(19 downto 0) := x"7FFF7";
constant c_ADDR_CRAM_OWNER : unsigned(19 downto 0) := x"7FFF3";
constant c_ADDR_USR_SET_REG : unsigned(19 downto 0) := x"7FFEF";
constant c_ADDR_USR_CLR_REG : unsigned(19 downto 0) := x"7FFEB";
constant c_ADDR_F7_ADER_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_ADDR_F7_ADER_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_ADDR_F7_ADER_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_ADDR_F7_ADER_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_ADDR_F6_ADER_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_ADDR_F6_ADER_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_ADDR_F6_ADER_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_ADDR_F6_ADER_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_ADDR_F5_ADER_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_ADDR_F5_ADER_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_ADDR_F5_ADER_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_ADDR_F5_ADER_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_ADDR_F4_ADER_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_ADDR_F4_ADER_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_ADDR_F4_ADER_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_ADDR_F4_ADER_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_ADDR_F3_ADER_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_ADDR_F3_ADER_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_ADDR_F3_ADER_2 : unsigned(19 downto 0) := x"7FF97";
constant c_ADDR_F3_ADER_3 : unsigned(19 downto 0) := x"7FF93";
constant c_ADDR_F2_ADER_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_ADDR_F2_ADER_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_ADDR_F2_ADER_2 : unsigned(19 downto 0) := x"7FF87";
constant c_ADDR_F2_ADER_3 : unsigned(19 downto 0) := x"7FF83";
constant c_ADDR_F1_ADER_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_ADDR_F1_ADER_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_ADDR_F1_ADER_2 : unsigned(19 downto 0) := x"7FF77";
constant c_ADDR_F1_ADER_3 : unsigned(19 downto 0) := x"7FF73";
constant c_ADDR_F0_ADER_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_ADDR_F0_ADER_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_ADDR_F0_ADER_2 : unsigned(19 downto 0) := x"7FF67";
constant c_ADDR_F0_ADER_3 : unsigned(19 downto 0) := x"7FF63";
-- User CSR addresses
constant c_ADDR_IRQ_VECTOR : unsigned(19 downto 0) := x"0002F";
constant c_ADDR_IRQ_LEVEL : unsigned(19 downto 0) := x"0002B";
constant c_ADDR_ENDIAN : unsigned(19 downto 0) := x"00023";
constant c_ADDR_TIME0_NS : unsigned(19 downto 0) := x"0001F";
constant c_ADDR_TIME1_NS : unsigned(19 downto 0) := x"0001B";
constant c_ADDR_TIME2_NS : unsigned(19 downto 0) := x"00017";
constant c_ADDR_TIME3_NS : unsigned(19 downto 0) := x"00013";
constant c_ADDR_TIME4_NS : unsigned(19 downto 0) := x"0000F";
constant c_ADDR_BYTES0 : unsigned(19 downto 0) := x"0000B";
constant c_ADDR_BYTES1 : unsigned(19 downto 0) := x"00007";
constant c_ADDR_WB32BITS : unsigned(19 downto 0) := x"00003";
------------------------------------------------------------------------------
-- Types
------------------------------------------------------------------------------
-- CR/CSR parameter arrays
type t_adem_array is array (integer range <>) of std_logic_vector( 31 downto 0);
type t_ader_array is array (integer range <>) of std_logic_vector( 31 downto 0);
type t_amcap_array is array (integer range <>) of std_logic_vector( 63 downto 0);
type t_xamcap_array is array (integer range <>) of std_logic_vector(255 downto 0);
type t_dawpr_array is array (integer range <>) of std_logic_vector( 7 downto 0);
type t_typeOfDataTransfer is (
D08_0,
D08_1,
......@@ -261,75 +210,6 @@ package vme64x_pack is
--TWOe_END_2
);
type t_FUNC_32b_array is
array (0 to 7) of unsigned(31 downto 0); -- ADER register array
type t_FUNC_64b_array is
array (0 to 7) of unsigned(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array is
array (0 to 7) of unsigned(255 downto 0); -- XAMCAP register array
type t_cr_array is
array (natural range <>) of std_logic_vector(7 downto 0);
------------------------------------------------------------------------------
-- Functions
------------------------------------------------------------------------------
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
revision_id : std_logic_vector( 31 downto 0);
program_id : std_logic_vector( 7 downto 0);
ascii_ptr : std_logic_vector( 23 downto 0);
beg_user_cr : std_logic_vector( 23 downto 0);
end_user_cr : std_logic_vector( 23 downto 0);
beg_cram : std_logic_vector( 23 downto 0);
end_cram : std_logic_vector( 23 downto 0);
beg_user_csr : std_logic_vector( 23 downto 0);
end_user_csr : std_logic_vector( 23 downto 0);
beg_sn : std_logic_vector( 23 downto 0);
end_sn : std_logic_vector( 23 downto 0);
f0_adem : std_logic_vector( 31 downto 0);
f0_amcap : std_logic_vector( 63 downto 0);
f0_xamcap : std_logic_vector(255 downto 0);
f0_dawpr : std_logic_vector( 7 downto 0);
f1_adem : std_logic_vector( 31 downto 0);
f1_amcap : std_logic_vector( 63 downto 0);
f1_xamcap : std_logic_vector(255 downto 0);
f1_dawpr : std_logic_vector( 7 downto 0);
f2_adem : std_logic_vector( 31 downto 0);
f2_amcap : std_logic_vector( 63 downto 0);
f2_xamcap : std_logic_vector(255 downto 0);
f2_dawpr : std_logic_vector( 7 downto 0);
f3_adem : std_logic_vector( 31 downto 0);
f3_amcap : std_logic_vector( 63 downto 0);
f3_xamcap : std_logic_vector(255 downto 0);
f3_dawpr : std_logic_vector( 7 downto 0);
f4_adem : std_logic_vector( 31 downto 0);
f4_amcap : std_logic_vector( 63 downto 0);
f4_xamcap : std_logic_vector(255 downto 0);
f4_dawpr : std_logic_vector( 7 downto 0);
f5_adem : std_logic_vector( 31 downto 0);
f5_amcap : std_logic_vector( 63 downto 0);
f5_xamcap : std_logic_vector(255 downto 0);
f5_dawpr : std_logic_vector( 7 downto 0);
f6_adem : std_logic_vector( 31 downto 0);
f6_amcap : std_logic_vector( 63 downto 0);
f6_xamcap : std_logic_vector(255 downto 0);
f6_dawpr : std_logic_vector( 7 downto 0);
f7_adem : std_logic_vector( 31 downto 0);
f7_amcap : std_logic_vector( 63 downto 0);
f7_xamcap : std_logic_vector(255 downto 0);
f7_dawpr : std_logic_vector( 7 downto 0)
) return t_cr_array;
function f_size (
A : std_logic_vector;
B : std_logic_vector
) return integer;
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
......@@ -435,6 +315,7 @@ package vme64x_pack is
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
......@@ -460,37 +341,7 @@ package vme64x_pack is
generic (
g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer;
g_BEG_USER_CR : std_logic_vector( 23 downto 0);
g_END_USER_CR : std_logic_vector( 23 downto 0);
g_BEG_CRAM : std_logic_vector( 23 downto 0);
g_END_CRAM : std_logic_vector( 23 downto 0);
g_BEG_USER_CSR : std_logic_vector( 23 downto 0);
g_END_USER_CSR : std_logic_vector( 23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0)
g_WB_ADDR_WIDTH : integer
);
port (
clk_i : in std_logic;
......@@ -527,102 +378,41 @@ package vme64x_pack is
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
addr_decoder_i : in std_logic_vector(63 downto 0);
addr_decoder_o : out std_logic_vector(63 downto 0);
decode_o : out std_logic;
am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0);
sel_i : in std_logic;
function_i : in std_logic_vector( 3 downto 0);
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
f0_ader_i : in std_logic_vector(31 downto 0);
f1_ader_i : in std_logic_vector(31 downto 0);
f2_ader_i : in std_logic_vector(31 downto 0);
f3_ader_i : in std_logic_vector(31 downto 0);
f4_ader_i : in std_logic_vector(31 downto 0);
f5_ader_i : in std_logic_vector(31 downto 0);
f6_ader_i : in std_logic_vector(31 downto 0);
f7_ader_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
);
end component VME_bus;
component VME_Access_Decode is
port (
clk_i : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
decode : in std_logic;
ModuleEnable : in std_logic;
Addr : in std_logic_vector(63 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
BAR_i : in std_logic_vector(4 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Funct_Sel : out std_logic_vector(7 downto 0);
Base_Addr : out std_logic_vector(63 downto 0);
Confaccess : out std_logic;
CardSel : out std_logic
);
end component VME_Access_Decode;
component VME_Funct_Match is
generic (
g_ADEM : t_adem_array(-1 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7)
);
port (
clk_i : in std_logic;
reset : in std_logic;
decode : in std_logic;
mainFSMreset : in std_logic;
Addr : in std_logic_vector(63 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
FunctMatch : out std_logic_vector(7 downto 0);
DFS_o : out std_logic_vector(7 downto 0);
Nx_Base_Addr : out std_logic_vector(63 downto 0)
clk_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(63 downto 0);
addr_o : out std_logic_vector(63 downto 0);
decode_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0);
xam_i : in std_logic_vector( 7 downto 0);
ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7);
sel_o : out std_logic;
function_o : out std_logic_vector( 3 downto 0)
);
end component VME_Funct_Match;
......@@ -641,38 +431,10 @@ package vme64x_pack is
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F0_DAWPR : std_logic_vector( 7 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F1_DAWPR : std_logic_vector( 7 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F2_DAWPR : std_logic_vector( 7 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F3_DAWPR : std_logic_vector( 7 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F4_DAWPR : std_logic_vector( 7 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F5_DAWPR : std_logic_vector( 7 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F6_DAWPR : std_logic_vector( 7 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0);
g_F7_DAWPR : std_logic_vector( 7 downto 0)
g_ADEM : t_adem_array(-1 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7);
g_DAWPR : t_dawpr_array(0 to 7)
);
port (
clk_i : in std_logic;
......@@ -694,70 +456,12 @@ package vme64x_pack is
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
f0_ader_o : out std_logic_vector(31 downto 0);
f1_ader_o : out std_logic_vector(31 downto 0);
f2_ader_o : out std_logic_vector(31 downto 0);
f3_ader_o : out std_logic_vector(31 downto 0);
f4_ader_o : out std_logic_vector(31 downto 0);
f5_ader_o : out std_logic_vector(31 downto 0);
f6_ader_o : out std_logic_vector(31 downto 0);
f7_ader_o : out std_logic_vector(31 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0);
f1_faf_ader_i : in std_logic_vector(31 downto 0);
f2_faf_ader_i : in std_logic_vector(31 downto 0);
f3_faf_ader_i : in std_logic_vector(31 downto 0);
f4_faf_ader_i : in std_logic_vector(31 downto 0);
f5_faf_ader_i : in std_logic_vector(31 downto 0);
f6_faf_ader_i : in std_logic_vector(31 downto 0);
f7_faf_ader_i : in std_logic_vector(31 downto 0);
f0_dfs_adem_i : in std_logic_vector(31 downto 0);
f1_dfs_adem_i : in std_logic_vector(31 downto 0);
f2_dfs_adem_i : in std_logic_vector(31 downto 0);
f3_dfs_adem_i : in std_logic_vector(31 downto 0);
f4_dfs_adem_i : in std_logic_vector(31 downto 0);
f5_dfs_adem_i : in std_logic_vector(31 downto 0);
f6_dfs_adem_i : in std_logic_vector(31 downto 0);
f7_dfs_adem_i : in std_logic_vector(31 downto 0)
ader_o : out t_ader_array(0 to 7);
faf_ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7)
);
end component VME_CR_CSR_Space;
component VME_Am_Match is
port (
clk_i : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
decode : in std_logic;
AmMatch : out std_logic_vector(7 downto 0)
);
end component VME_Am_Match;
component VME_User_CSR is
generic (
g_WB_DATA_WIDTH : integer
......@@ -841,546 +545,8 @@ package vme64x_pack is
);
end component;
component VME_CRAM is
generic (
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0)
);
port (
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0)
);
end component VME_CRAM;
end vme64x_pack;
package body vme64x_pack is
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
revision_id : std_logic_vector( 31 downto 0);
program_id : std_logic_vector( 7 downto 0);
ascii_ptr : std_logic_vector( 23 downto 0);
beg_user_cr : std_logic_vector( 23 downto 0);
end_user_cr : std_logic_vector( 23 downto 0);
beg_cram : std_logic_vector( 23 downto 0);
end_cram : std_logic_vector( 23 downto 0);
beg_user_csr : std_logic_vector( 23 downto 0);
end_user_csr : std_logic_vector( 23 downto 0);
beg_sn : std_logic_vector( 23 downto 0);
end_sn : std_logic_vector( 23 downto 0);
f0_adem : std_logic_vector( 31 downto 0);
f0_amcap : std_logic_vector( 63 downto 0);
f0_xamcap : std_logic_vector(255 downto 0);
f0_dawpr : std_logic_vector( 7 downto 0);
f1_adem : std_logic_vector( 31 downto 0);
f1_amcap : std_logic_vector( 63 downto 0);
f1_xamcap : std_logic_vector(255 downto 0);
f1_dawpr : std_logic_vector( 7 downto 0);
f2_adem : std_logic_vector( 31 downto 0);
f2_amcap : std_logic_vector( 63 downto 0);
f2_xamcap : std_logic_vector(255 downto 0);
f2_dawpr : std_logic_vector( 7 downto 0);
f3_adem : std_logic_vector( 31 downto 0);
f3_amcap : std_logic_vector( 63 downto 0);
f3_xamcap : std_logic_vector(255 downto 0);
f3_dawpr : std_logic_vector( 7 downto 0);
f4_adem : std_logic_vector( 31 downto 0);
f4_amcap : std_logic_vector( 63 downto 0);
f4_xamcap : std_logic_vector(255 downto 0);
f4_dawpr : std_logic_vector( 7 downto 0);
f5_adem : std_logic_vector( 31 downto 0);
f5_amcap : std_logic_vector( 63 downto 0);
f5_xamcap : std_logic_vector(255 downto 0);
f5_dawpr : std_logic_vector( 7 downto 0);
f6_adem : std_logic_vector( 31 downto 0);
f6_amcap : std_logic_vector( 63 downto 0);
f6_xamcap : std_logic_vector(255 downto 0);
f6_dawpr : std_logic_vector( 7 downto 0);
f7_adem : std_logic_vector( 31 downto 0);
f7_amcap : std_logic_vector( 63 downto 0);
f7_xamcap : std_logic_vector(255 downto 0);
f7_dawpr : std_logic_vector( 7 downto 0)
) return t_cr_array
is
variable cr : t_cr_array(1023 downto 0) := (others => x"00");
variable crc : unsigned(7 downto 0) := x"00";
begin
cr(16#001#) := x"00"; -- Length of CR (excluding CRC)
cr(16#002#) := x"03";
cr(16#003#) := x"ff";
cr(16#004#) := x"81"; -- CR data access width
cr(16#005#) := x"81"; -- CSR data access width
cr(16#006#) := x"02"; -- CR/CSR Space Specification ID
cr(16#007#) := x"43"; -- ASCII "C"
cr(16#008#) := x"52"; -- ASCII "R"
cr(16#009#) := manufacturer_id(23 downto 16);
cr(16#00A#) := manufacturer_id(15 downto 8);
cr(16#00B#) := manufacturer_id( 7 downto 0);
cr(16#00C#) := board_id(31 downto 24);
cr(16#00D#) := board_id(23 downto 16);
cr(16#00E#) := board_id(15 downto 8);
cr(16#00F#) := board_id( 7 downto 0);
cr(16#010#) := revision_id(31 downto 24);
cr(16#011#) := revision_id(23 downto 16);
cr(16#012#) := revision_id(15 downto 8);
cr(16#013#) := revision_id( 7 downto 0);
cr(16#014#) := ascii_ptr(23 downto 16);
cr(16#015#) := ascii_ptr(15 downto 8);
cr(16#016#) := ascii_ptr( 7 downto 0);
cr(16#01F#) := program_id;
cr(16#020#) := beg_user_cr(23 downto 16);
cr(16#021#) := beg_user_cr(15 downto 8);
cr(16#022#) := beg_user_cr( 7 downto 0);
cr(16#023#) := end_user_cr(23 downto 16);
cr(16#024#) := end_user_cr(15 downto 8);
cr(16#025#) := end_user_cr( 7 downto 0);
cr(16#026#) := beg_cram(23 downto 16);
cr(16#027#) := beg_cram(15 downto 8);
cr(16#028#) := beg_cram( 7 downto 0);
cr(16#029#) := end_cram(23 downto 16);
cr(16#02A#) := end_cram(15 downto 8);
cr(16#02B#) := end_cram( 7 downto 0);
cr(16#02C#) := beg_user_csr(23 downto 16);
cr(16#02D#) := beg_user_csr(15 downto 8);
cr(16#02E#) := beg_user_csr( 7 downto 0);
cr(16#02F#) := end_user_csr(23 downto 16);
cr(16#030#) := end_user_csr(15 downto 8);
cr(16#031#) := end_user_csr( 7 downto 0);
cr(16#032#) := beg_sn(23 downto 16);
cr(16#033#) := beg_sn(15 downto 8);
cr(16#034#) := beg_sn( 7 downto 0);
cr(16#035#) := end_sn(23 downto 16);
cr(16#036#) := end_sn(15 downto 8);
cr(16#037#) := end_sn( 7 downto 0);
cr(16#038#) := x"04"; -- Slave characteristics parameter
cr(16#039#) := x"00"; -- User-defined slave characteristics parameter
cr(16#03D#) := x"0E"; -- Interrupter capabilities
cr(16#03F#) := x"81"; -- CRAM data access width
cr(16#040#) := f0_dawpr;
cr(16#041#) := f1_dawpr;
cr(16#042#) := f2_dawpr;
cr(16#043#) := f3_dawpr;
cr(16#044#) := f4_dawpr;
cr(16#045#) := f5_dawpr;
cr(16#046#) := f6_dawpr;
cr(16#047#) := f7_dawpr;
cr(16#048#) := f0_amcap(63 downto 56);
cr(16#049#) := f0_amcap(55 downto 48);
cr(16#04A#) := f0_amcap(47 downto 40);
cr(16#04B#) := f0_amcap(39 downto 32);
cr(16#04C#) := f0_amcap(31 downto 24);
cr(16#04D#) := f0_amcap(23 downto 16);
cr(16#04E#) := f0_amcap(15 downto 8);
cr(16#04F#) := f0_amcap( 7 downto 0);
cr(16#050#) := f1_amcap(63 downto 56);
cr(16#051#) := f1_amcap(55 downto 48);
cr(16#052#) := f1_amcap(47 downto 40);
cr(16#053#) := f1_amcap(39 downto 32);
cr(16#054#) := f1_amcap(31 downto 24);
cr(16#055#) := f1_amcap(23 downto 16);
cr(16#056#) := f1_amcap(15 downto 8);
cr(16#057#) := f1_amcap( 7 downto 0);
cr(16#058#) := f2_amcap(63 downto 56);
cr(16#059#) := f2_amcap(55 downto 48);
cr(16#05A#) := f2_amcap(47 downto 40);
cr(16#05B#) := f2_amcap(39 downto 32);
cr(16#05C#) := f2_amcap(31 downto 24);
cr(16#05D#) := f2_amcap(23 downto 16);
cr(16#05E#) := f2_amcap(15 downto 8);
cr(16#05F#) := f2_amcap( 7 downto 0);
cr(16#060#) := f3_amcap(63 downto 56);
cr(16#061#) := f3_amcap(55 downto 48);
cr(16#062#) := f3_amcap(47 downto 40);
cr(16#063#) := f3_amcap(39 downto 32);
cr(16#064#) := f3_amcap(31 downto 24);
cr(16#065#) := f3_amcap(23 downto 16);
cr(16#066#) := f3_amcap(15 downto 8);
cr(16#067#) := f3_amcap( 7 downto 0);
cr(16#068#) := f4_amcap(63 downto 56);
cr(16#069#) := f4_amcap(55 downto 48);
cr(16#06A#) := f4_amcap(47 downto 40);
cr(16#06B#) := f4_amcap(39 downto 32);
cr(16#06C#) := f4_amcap(31 downto 24);
cr(16#06D#) := f4_amcap(23 downto 16);
cr(16#06E#) := f4_amcap(15 downto 8);
cr(16#06F#) := f4_amcap( 7 downto 0);
cr(16#070#) := f5_amcap(63 downto 56);
cr(16#071#) := f5_amcap(55 downto 48);
cr(16#072#) := f5_amcap(47 downto 40);
cr(16#073#) := f5_amcap(39 downto 32);
cr(16#074#) := f5_amcap(31 downto 24);
cr(16#075#) := f5_amcap(23 downto 16);
cr(16#076#) := f5_amcap(15 downto 8);
cr(16#077#) := f5_amcap( 7 downto 0);
cr(16#078#) := f6_amcap(63 downto 56);
cr(16#079#) := f6_amcap(55 downto 48);
cr(16#07A#) := f6_amcap(47 downto 40);
cr(16#07B#) := f6_amcap(39 downto 32);
cr(16#07C#) := f6_amcap(31 downto 24);
cr(16#07D#) := f6_amcap(23 downto 16);
cr(16#07E#) := f6_amcap(15 downto 8);
cr(16#07F#) := f6_amcap( 7 downto 0);
cr(16#080#) := f7_amcap(63 downto 56);
cr(16#081#) := f7_amcap(55 downto 48);
cr(16#082#) := f7_amcap(47 downto 40);
cr(16#083#) := f7_amcap(39 downto 32);
cr(16#084#) := f7_amcap(31 downto 24);
cr(16#085#) := f7_amcap(23 downto 16);
cr(16#086#) := f7_amcap(15 downto 8);
cr(16#087#) := f7_amcap( 7 downto 0);
cr(16#088#) := f0_xamcap(255 downto 248);
cr(16#089#) := f0_xamcap(247 downto 240);
cr(16#08A#) := f0_xamcap(239 downto 232);
cr(16#08B#) := f0_xamcap(231 downto 224);
cr(16#08C#) := f0_xamcap(223 downto 216);
cr(16#08D#) := f0_xamcap(215 downto 208);
cr(16#08E#) := f0_xamcap(207 downto 200);
cr(16#08F#) := f0_xamcap(199 downto 192);
cr(16#090#) := f0_xamcap(191 downto 184);
cr(16#091#) := f0_xamcap(183 downto 176);
cr(16#092#) := f0_xamcap(175 downto 168);
cr(16#093#) := f0_xamcap(167 downto 160);
cr(16#094#) := f0_xamcap(159 downto 152);
cr(16#095#) := f0_xamcap(151 downto 144);
cr(16#096#) := f0_xamcap(143 downto 136);
cr(16#097#) := f0_xamcap(135 downto 128);
cr(16#098#) := f0_xamcap(127 downto 120);
cr(16#099#) := f0_xamcap(119 downto 112);
cr(16#09A#) := f0_xamcap(111 downto 104);
cr(16#09B#) := f0_xamcap(103 downto 96);
cr(16#09C#) := f0_xamcap( 95 downto 88);
cr(16#09D#) := f0_xamcap( 87 downto 80);
cr(16#09E#) := f0_xamcap( 79 downto 72);
cr(16#09F#) := f0_xamcap( 71 downto 64);
cr(16#0A0#) := f0_xamcap( 63 downto 56);
cr(16#0A1#) := f0_xamcap( 55 downto 48);
cr(16#0A2#) := f0_xamcap( 47 downto 40);
cr(16#0A3#) := f0_xamcap( 39 downto 32);
cr(16#0A4#) := f0_xamcap( 31 downto 24);
cr(16#0A5#) := f0_xamcap( 23 downto 16);
cr(16#0A6#) := f0_xamcap( 15 downto 8);
cr(16#0A7#) := f0_xamcap( 7 downto 0);
cr(16#0A8#) := f1_xamcap(255 downto 248);
cr(16#0A9#) := f1_xamcap(247 downto 240);
cr(16#0AA#) := f1_xamcap(239 downto 232);
cr(16#0AB#) := f1_xamcap(231 downto 224);
cr(16#0AC#) := f1_xamcap(223 downto 216);
cr(16#0AD#) := f1_xamcap(215 downto 208);
cr(16#0AE#) := f1_xamcap(207 downto 200);
cr(16#0AF#) := f1_xamcap(199 downto 192);
cr(16#0B0#) := f1_xamcap(191 downto 184);
cr(16#0B1#) := f1_xamcap(183 downto 176);
cr(16#0B2#) := f1_xamcap(175 downto 168);
cr(16#0B3#) := f1_xamcap(167 downto 160);
cr(16#0B4#) := f1_xamcap(159 downto 152);
cr(16#0B5#) := f1_xamcap(151 downto 144);
cr(16#0B6#) := f1_xamcap(143 downto 136);
cr(16#0B7#) := f1_xamcap(135 downto 128);
cr(16#0B8#) := f1_xamcap(127 downto 120);
cr(16#0B9#) := f1_xamcap(119 downto 112);
cr(16#0BA#) := f1_xamcap(111 downto 104);
cr(16#0BB#) := f1_xamcap(103 downto 96);
cr(16#0BC#) := f1_xamcap( 95 downto 88);
cr(16#0BD#) := f1_xamcap( 87 downto 80);
cr(16#0BE#) := f1_xamcap( 79 downto 72);
cr(16#0BF#) := f1_xamcap( 71 downto 64);
cr(16#0C0#) := f1_xamcap( 63 downto 56);
cr(16#0C1#) := f1_xamcap( 55 downto 48);
cr(16#0C2#) := f1_xamcap( 47 downto 40);
cr(16#0C3#) := f1_xamcap( 39 downto 32);
cr(16#0C4#) := f1_xamcap( 31 downto 24);
cr(16#0C5#) := f1_xamcap( 23 downto 16);
cr(16#0C6#) := f1_xamcap( 15 downto 8);
cr(16#0C7#) := f1_xamcap( 7 downto 0);
cr(16#0C8#) := f2_xamcap(255 downto 248);
cr(16#0C9#) := f2_xamcap(247 downto 240);
cr(16#0CA#) := f2_xamcap(239 downto 232);
cr(16#0CB#) := f2_xamcap(231 downto 224);
cr(16#0CC#) := f2_xamcap(223 downto 216);
cr(16#0CD#) := f2_xamcap(215 downto 208);
cr(16#0CE#) := f2_xamcap(207 downto 200);
cr(16#0CF#) := f2_xamcap(199 downto 192);
cr(16#0D0#) := f2_xamcap(191 downto 184);
cr(16#0D1#) := f2_xamcap(183 downto 176);
cr(16#0D2#) := f2_xamcap(175 downto 168);
cr(16#0D3#) := f2_xamcap(167 downto 160);
cr(16#0D4#) := f2_xamcap(159 downto 152);
cr(16#0D5#) := f2_xamcap(151 downto 144);
cr(16#0D6#) := f2_xamcap(143 downto 136);
cr(16#0D7#) := f2_xamcap(135 downto 128);
cr(16#0D8#) := f2_xamcap(127 downto 120);
cr(16#0D9#) := f2_xamcap(119 downto 112);
cr(16#0DA#) := f2_xamcap(111 downto 104);
cr(16#0DB#) := f2_xamcap(103 downto 96);
cr(16#0DC#) := f2_xamcap( 95 downto 88);
cr(16#0DD#) := f2_xamcap( 87 downto 80);
cr(16#0DE#) := f2_xamcap( 79 downto 72);
cr(16#0DF#) := f2_xamcap( 71 downto 64);
cr(16#0E0#) := f2_xamcap( 63 downto 56);
cr(16#0E1#) := f2_xamcap( 55 downto 48);
cr(16#0E2#) := f2_xamcap( 47 downto 40);
cr(16#0E3#) := f2_xamcap( 39 downto 32);
cr(16#0E4#) := f2_xamcap( 31 downto 24);
cr(16#0E5#) := f2_xamcap( 23 downto 16);
cr(16#0E6#) := f2_xamcap( 15 downto 8);
cr(16#0E7#) := f2_xamcap( 7 downto 0);
cr(16#0E8#) := f3_xamcap(255 downto 248);
cr(16#0E9#) := f3_xamcap(247 downto 240);
cr(16#0EA#) := f3_xamcap(239 downto 232);
cr(16#0EB#) := f3_xamcap(231 downto 224);
cr(16#0EC#) := f3_xamcap(223 downto 216);
cr(16#0ED#) := f3_xamcap(215 downto 208);
cr(16#0EE#) := f3_xamcap(207 downto 200);
cr(16#0EF#) := f3_xamcap(199 downto 192);
cr(16#0F0#) := f3_xamcap(191 downto 184);
cr(16#0F1#) := f3_xamcap(183 downto 176);
cr(16#0F2#) := f3_xamcap(175 downto 168);
cr(16#0F3#) := f3_xamcap(167 downto 160);
cr(16#0F4#) := f3_xamcap(159 downto 152);
cr(16#0F5#) := f3_xamcap(151 downto 144);
cr(16#0F6#) := f3_xamcap(143 downto 136);
cr(16#0F7#) := f3_xamcap(135 downto 128);
cr(16#0F8#) := f3_xamcap(127 downto 120);
cr(16#0F9#) := f3_xamcap(119 downto 112);
cr(16#0FA#) := f3_xamcap(111 downto 104);
cr(16#0FB#) := f3_xamcap(103 downto 96);
cr(16#0FC#) := f3_xamcap( 95 downto 88);
cr(16#0FD#) := f3_xamcap( 87 downto 80);
cr(16#0FE#) := f3_xamcap( 79 downto 72);
cr(16#0FF#) := f3_xamcap( 71 downto 64);
cr(16#100#) := f3_xamcap( 63 downto 56);
cr(16#101#) := f3_xamcap( 55 downto 48);
cr(16#102#) := f3_xamcap( 47 downto 40);
cr(16#103#) := f3_xamcap( 39 downto 32);
cr(16#104#) := f3_xamcap( 31 downto 24);
cr(16#105#) := f3_xamcap( 23 downto 16);
cr(16#106#) := f3_xamcap( 15 downto 8);
cr(16#107#) := f3_xamcap( 7 downto 0);
cr(16#108#) := f4_xamcap(255 downto 248);
cr(16#109#) := f4_xamcap(247 downto 240);
cr(16#10A#) := f4_xamcap(239 downto 232);
cr(16#10B#) := f4_xamcap(231 downto 224);
cr(16#10C#) := f4_xamcap(223 downto 216);
cr(16#10D#) := f4_xamcap(215 downto 208);
cr(16#10E#) := f4_xamcap(207 downto 200);
cr(16#10F#) := f4_xamcap(199 downto 192);
cr(16#110#) := f4_xamcap(191 downto 184);
cr(16#111#) := f4_xamcap(183 downto 176);
cr(16#112#) := f4_xamcap(175 downto 168);
cr(16#113#) := f4_xamcap(167 downto 160);
cr(16#114#) := f4_xamcap(159 downto 152);
cr(16#115#) := f4_xamcap(151 downto 144);
cr(16#116#) := f4_xamcap(143 downto 136);
cr(16#117#) := f4_xamcap(135 downto 128);
cr(16#118#) := f4_xamcap(127 downto 120);
cr(16#119#) := f4_xamcap(119 downto 112);
cr(16#11A#) := f4_xamcap(111 downto 104);
cr(16#11B#) := f4_xamcap(103 downto 96);
cr(16#11C#) := f4_xamcap( 95 downto 88);
cr(16#11D#) := f4_xamcap( 87 downto 80);
cr(16#11E#) := f4_xamcap( 79 downto 72);
cr(16#11F#) := f4_xamcap( 71 downto 64);
cr(16#120#) := f4_xamcap( 63 downto 56);
cr(16#121#) := f4_xamcap( 55 downto 48);
cr(16#122#) := f4_xamcap( 47 downto 40);
cr(16#123#) := f4_xamcap( 39 downto 32);
cr(16#124#) := f4_xamcap( 31 downto 24);
cr(16#125#) := f4_xamcap( 23 downto 16);
cr(16#126#) := f4_xamcap( 15 downto 8);
cr(16#127#) := f4_xamcap( 7 downto 0);
cr(16#128#) := f5_xamcap(255 downto 248);
cr(16#129#) := f5_xamcap(247 downto 240);
cr(16#12A#) := f5_xamcap(239 downto 232);
cr(16#12B#) := f5_xamcap(231 downto 224);
cr(16#12C#) := f5_xamcap(223 downto 216);
cr(16#12D#) := f5_xamcap(215 downto 208);
cr(16#12E#) := f5_xamcap(207 downto 200);
cr(16#12F#) := f5_xamcap(199 downto 192);
cr(16#130#) := f5_xamcap(191 downto 184);
cr(16#131#) := f5_xamcap(183 downto 176);
cr(16#132#) := f5_xamcap(175 downto 168);
cr(16#133#) := f5_xamcap(167 downto 160);
cr(16#134#) := f5_xamcap(159 downto 152);
cr(16#135#) := f5_xamcap(151 downto 144);
cr(16#136#) := f5_xamcap(143 downto 136);
cr(16#137#) := f5_xamcap(135 downto 128);
cr(16#138#) := f5_xamcap(127 downto 120);
cr(16#139#) := f5_xamcap(119 downto 112);
cr(16#13A#) := f5_xamcap(111 downto 104);
cr(16#13B#) := f5_xamcap(103 downto 96);
cr(16#13C#) := f5_xamcap( 95 downto 88);
cr(16#13D#) := f5_xamcap( 87 downto 80);
cr(16#13E#) := f5_xamcap( 79 downto 72);
cr(16#13F#) := f5_xamcap( 71 downto 64);
cr(16#140#) := f5_xamcap( 63 downto 56);
cr(16#141#) := f5_xamcap( 55 downto 48);
cr(16#142#) := f5_xamcap( 47 downto 40);
cr(16#143#) := f5_xamcap( 39 downto 32);
cr(16#144#) := f5_xamcap( 31 downto 24);
cr(16#145#) := f5_xamcap( 23 downto 16);
cr(16#146#) := f5_xamcap( 15 downto 8);
cr(16#147#) := f5_xamcap( 7 downto 0);
cr(16#148#) := f6_xamcap(255 downto 248);
cr(16#149#) := f6_xamcap(247 downto 240);
cr(16#14A#) := f6_xamcap(239 downto 232);
cr(16#14B#) := f6_xamcap(231 downto 224);
cr(16#14C#) := f6_xamcap(223 downto 216);
cr(16#14D#) := f6_xamcap(215 downto 208);
cr(16#14E#) := f6_xamcap(207 downto 200);
cr(16#14F#) := f6_xamcap(199 downto 192);
cr(16#150#) := f6_xamcap(191 downto 184);
cr(16#151#) := f6_xamcap(183 downto 176);
cr(16#152#) := f6_xamcap(175 downto 168);
cr(16#153#) := f6_xamcap(167 downto 160);
cr(16#154#) := f6_xamcap(159 downto 152);
cr(16#155#) := f6_xamcap(151 downto 144);
cr(16#156#) := f6_xamcap(143 downto 136);
cr(16#157#) := f6_xamcap(135 downto 128);
cr(16#158#) := f6_xamcap(127 downto 120);
cr(16#159#) := f6_xamcap(119 downto 112);
cr(16#15A#) := f6_xamcap(111 downto 104);
cr(16#15B#) := f6_xamcap(103 downto 96);
cr(16#15C#) := f6_xamcap( 95 downto 88);
cr(16#15D#) := f6_xamcap( 87 downto 80);
cr(16#15E#) := f6_xamcap( 79 downto 72);
cr(16#15F#) := f6_xamcap( 71 downto 64);
cr(16#160#) := f6_xamcap( 63 downto 56);
cr(16#161#) := f6_xamcap( 55 downto 48);
cr(16#162#) := f6_xamcap( 47 downto 40);
cr(16#163#) := f6_xamcap( 39 downto 32);
cr(16#164#) := f6_xamcap( 31 downto 24);
cr(16#165#) := f6_xamcap( 23 downto 16);
cr(16#166#) := f6_xamcap( 15 downto 8);
cr(16#167#) := f6_xamcap( 7 downto 0);
cr(16#168#) := f7_xamcap(255 downto 248);
cr(16#169#) := f7_xamcap(247 downto 240);
cr(16#16A#) := f7_xamcap(239 downto 232);
cr(16#16B#) := f7_xamcap(231 downto 224);
cr(16#16C#) := f7_xamcap(223 downto 216);
cr(16#16D#) := f7_xamcap(215 downto 208);
cr(16#16E#) := f7_xamcap(207 downto 200);
cr(16#16F#) := f7_xamcap(199 downto 192);
cr(16#170#) := f7_xamcap(191 downto 184);
cr(16#171#) := f7_xamcap(183 downto 176);
cr(16#172#) := f7_xamcap(175 downto 168);
cr(16#173#) := f7_xamcap(167 downto 160);
cr(16#174#) := f7_xamcap(159 downto 152);
cr(16#175#) := f7_xamcap(151 downto 144);
cr(16#176#) := f7_xamcap(143 downto 136);
cr(16#177#) := f7_xamcap(135 downto 128);
cr(16#178#) := f7_xamcap(127 downto 120);
cr(16#179#) := f7_xamcap(119 downto 112);
cr(16#17A#) := f7_xamcap(111 downto 104);
cr(16#17B#) := f7_xamcap(103 downto 96);
cr(16#17C#) := f7_xamcap( 95 downto 88);
cr(16#17D#) := f7_xamcap( 87 downto 80);
cr(16#17E#) := f7_xamcap( 79 downto 72);
cr(16#17F#) := f7_xamcap( 71 downto 64);
cr(16#180#) := f7_xamcap( 63 downto 56);
cr(16#181#) := f7_xamcap( 55 downto 48);
cr(16#182#) := f7_xamcap( 47 downto 40);
cr(16#183#) := f7_xamcap( 39 downto 32);
cr(16#184#) := f7_xamcap( 31 downto 24);
cr(16#185#) := f7_xamcap( 23 downto 16);
cr(16#186#) := f7_xamcap( 15 downto 8);
cr(16#187#) := f7_xamcap( 7 downto 0);
cr(16#188#) := f0_adem(31 downto 24);
cr(16#189#) := f0_adem(23 downto 16);
cr(16#18A#) := f0_adem(15 downto 8);
cr(16#18B#) := f0_adem( 7 downto 0);
cr(16#18C#) := f1_adem(31 downto 24);
cr(16#18D#) := f1_adem(23 downto 16);
cr(16#18E#) := f1_adem(15 downto 8);
cr(16#18F#) := f1_adem( 7 downto 0);
cr(16#190#) := f2_adem(31 downto 24);
cr(16#191#) := f2_adem(23 downto 16);
cr(16#192#) := f2_adem(15 downto 8);
cr(16#193#) := f2_adem( 7 downto 0);
cr(16#194#) := f3_adem(31 downto 24);
cr(16#195#) := f3_adem(23 downto 16);
cr(16#196#) := f3_adem(15 downto 8);
cr(16#197#) := f3_adem( 7 downto 0);
cr(16#198#) := f4_adem(31 downto 24);
cr(16#199#) := f4_adem(23 downto 16);
cr(16#19A#) := f4_adem(15 downto 8);
cr(16#19B#) := f4_adem( 7 downto 0);
cr(16#19C#) := f5_adem(31 downto 24);
cr(16#19D#) := f5_adem(23 downto 16);
cr(16#19E#) := f5_adem(15 downto 8);
cr(16#19F#) := f5_adem( 7 downto 0);
cr(16#1A0#) := f6_adem(31 downto 24);
cr(16#1A1#) := f6_adem(23 downto 16);
cr(16#1A2#) := f6_adem(15 downto 8);
cr(16#1A3#) := f6_adem( 7 downto 0);
cr(16#1A4#) := f7_adem(31 downto 24);
cr(16#1A5#) := f7_adem(23 downto 16);
cr(16#1A6#) := f7_adem(15 downto 8);
cr(16#1A7#) := f7_adem( 7 downto 0);
-- Calculate CRC
for i in 1 to cr'length-1 loop
crc := crc + unsigned(cr(i));
end loop;
cr(16#000#) := std_logic_vector(crc);
return cr;
end;
function f_size (
A : std_logic_vector;
B : std_logic_vector
) return integer is
begin
return ((to_integer(unsigned(B)) - to_integer(unsigned(A))) / 4) + 1;
end;
end vme64x_pack;
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 72eff0ad
......@@ -142,6 +142,7 @@ entity xvme64x_core is
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
......@@ -275,6 +276,7 @@ begin -- wrapper
STALL_i => master_i.stall,
endian_i => endian_i,
function_o => function_o,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
......
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ 72eff0ad
......@@ -54,7 +54,6 @@ package xvme64x_core_pkg is
type t_vme64x_out is record
iackout_n : std_logic;
dtack_oe : std_logic;
dtack_n : std_logic;
data_dir : std_logic;
......@@ -164,6 +163,7 @@ package xvme64x_core_pkg is
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
......
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