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VME64x core
Commits
72eff0ad
Commit
72eff0ad
authored
Aug 26, 2017
by
Tom Levens
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12 changed files
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-2339
Manifest.py
hdl/vme64x-core/rtl/Manifest.py
+0
-3
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+148
-173
VME_Access_Decode.vhd
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
+0
-314
VME_Am_Match.vhd
hdl/vme64x-core/rtl/VME_Am_Match.vhd
+0
-180
VME_CRAM.vhd
hdl/vme64x-core/rtl/VME_CRAM.vhd
+0
-77
VME_CR_CSR_Space.vhd
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+260
-260
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+353
-287
VME_User_CSR.vhd
hdl/vme64x-core/rtl/VME_User_CSR.vhd
+44
-32
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+54
-129
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+49
-883
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+2
-0
xvme64x_core_pkg.vhd
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+1
-1
No files found.
hdl/vme64x-core/rtl/Manifest.py
View file @
72eff0ad
...
@@ -2,12 +2,9 @@ files = [ "xvme64x_core.vhd",
...
@@ -2,12 +2,9 @@ files = [ "xvme64x_core.vhd",
"xvme64x_core_pkg.vhd"
,
"xvme64x_core_pkg.vhd"
,
"VME64xCore_Top.vhd"
,
"VME64xCore_Top.vhd"
,
"vme64x_pack.vhd"
,
"vme64x_pack.vhd"
,
"VME_Access_Decode.vhd"
,
"VME_Am_Match.vhd"
,
"VME_bus.vhd"
,
"VME_bus.vhd"
,
"VME_CR_CSR_Space.vhd"
,
"VME_CR_CSR_Space.vhd"
,
"VME_User_CSR.vhd"
,
"VME_User_CSR.vhd"
,
"VME_CRAM.vhd"
,
"VME_Funct_Match.vhd"
,
"VME_Funct_Match.vhd"
,
"VME_IRQ_Controller.vhd"
,
"VME_IRQ_Controller.vhd"
,
"VME_swapper.vhd"
,
"VME_swapper.vhd"
,
...
...
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
72eff0ad
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
deleted
100644 → 0
View file @
a3b2fde3
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/VME_Am_Match.vhd
deleted
100644 → 0
View file @
a3b2fde3
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Am_Match (VME_Am_Match.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This component checks if the AM match. If it is the correspondent AmMatch's
-- bit is asserted. This condition is necessary but not sufficient to select
-- the function and access the board.
--
-- If DFS = '0' the function supports only access modes with the same address
-- width;
-- 1 function --> only 1 address width;
-- with address width I mean A16, A24, A32 or A64.
-- is sufficient check the AMCAP;
-- AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
--
-- If DFS = '1' the function supports access modes with different address
-- widths so AmMatch(i) is asserted only if ADER[7:2] = AM and
-- s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
--
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if
-- AM = 0x20 and if the -- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if
-- DFS = '1' also ADER[9:2] must be equal -- to XAM[7:0] lines.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
vme64x_pack
.
all
;
entity
VME_Am_Match
is
port
(
clk_i
:
in
std_logic
;
reset
:
in
std_logic
;
mainFSMreset
:
in
std_logic
;
Ader0
:
in
std_logic_vector
(
31
downto
0
);
Ader1
:
in
std_logic_vector
(
31
downto
0
);
Ader2
:
in
std_logic_vector
(
31
downto
0
);
Ader3
:
in
std_logic_vector
(
31
downto
0
);
Ader4
:
in
std_logic_vector
(
31
downto
0
);
Ader5
:
in
std_logic_vector
(
31
downto
0
);
Ader6
:
in
std_logic_vector
(
31
downto
0
);
Ader7
:
in
std_logic_vector
(
31
downto
0
);
AmCap0
:
in
std_logic_vector
(
63
downto
0
);
AmCap1
:
in
std_logic_vector
(
63
downto
0
);
AmCap2
:
in
std_logic_vector
(
63
downto
0
);
AmCap3
:
in
std_logic_vector
(
63
downto
0
);
AmCap4
:
in
std_logic_vector
(
63
downto
0
);
AmCap5
:
in
std_logic_vector
(
63
downto
0
);
AmCap6
:
in
std_logic_vector
(
63
downto
0
);
AmCap7
:
in
std_logic_vector
(
63
downto
0
);
XAmCap0
:
in
std_logic_vector
(
255
downto
0
);
XAmCap1
:
in
std_logic_vector
(
255
downto
0
);
XAmCap2
:
in
std_logic_vector
(
255
downto
0
);
XAmCap3
:
in
std_logic_vector
(
255
downto
0
);
XAmCap4
:
in
std_logic_vector
(
255
downto
0
);
XAmCap5
:
in
std_logic_vector
(
255
downto
0
);
XAmCap6
:
in
std_logic_vector
(
255
downto
0
);
XAmCap7
:
in
std_logic_vector
(
255
downto
0
);
Am
:
in
std_logic_vector
(
5
downto
0
);
XAm
:
in
std_logic_vector
(
7
downto
0
);
DFS_i
:
in
std_logic_vector
(
7
downto
0
);
decode
:
in
std_logic
;
AmMatch
:
out
std_logic_vector
(
7
downto
0
)
);
end
VME_Am_Match
;
architecture
Behavioral
of
VME_Am_Match
is
signal
s_FUNC_ADER
:
t_FUNC_32b_array
;
signal
s_FUNC_AMCAP
:
t_FUNC_64b_array
;
signal
s_FUNC_XAMCAP
:
t_FUNC_256b_array
;
signal
s_amcap_match
:
std_logic_vector
(
7
downto
0
);
signal
s_xamcap_match
:
std_logic_vector
(
7
downto
0
);
begin
s_FUNC_ADER
(
0
)
<=
unsigned
(
Ader0
);
s_FUNC_ADER
(
1
)
<=
unsigned
(
Ader1
);
s_FUNC_ADER
(
2
)
<=
unsigned
(
Ader2
);
s_FUNC_ADER
(
3
)
<=
unsigned
(
Ader3
);
s_FUNC_ADER
(
4
)
<=
unsigned
(
Ader4
);
s_FUNC_ADER
(
5
)
<=
unsigned
(
Ader5
);
s_FUNC_ADER
(
6
)
<=
unsigned
(
Ader6
);
s_FUNC_ADER
(
7
)
<=
unsigned
(
Ader7
);
s_FUNC_AMCAP
(
0
)
<=
unsigned
(
AmCap0
);
s_FUNC_AMCAP
(
1
)
<=
unsigned
(
AmCap1
);
s_FUNC_AMCAP
(
2
)
<=
unsigned
(
AmCap2
);
s_FUNC_AMCAP
(
3
)
<=
unsigned
(
AmCap3
);
s_FUNC_AMCAP
(
4
)
<=
unsigned
(
AmCap4
);
s_FUNC_AMCAP
(
5
)
<=
unsigned
(
AmCap5
);
s_FUNC_AMCAP
(
6
)
<=
unsigned
(
AmCap6
);
s_FUNC_AMCAP
(
7
)
<=
unsigned
(
AmCap7
);
s_FUNC_XAMCAP
(
0
)
<=
unsigned
(
XAmCap0
);
s_FUNC_XAMCAP
(
1
)
<=
unsigned
(
XAmCap1
);
s_FUNC_XAMCAP
(
2
)
<=
unsigned
(
XAmCap2
);
s_FUNC_XAMCAP
(
3
)
<=
unsigned
(
XAmCap3
);
s_FUNC_XAMCAP
(
4
)
<=
unsigned
(
XAmCap4
);
s_FUNC_XAMCAP
(
5
)
<=
unsigned
(
XAmCap5
);
s_FUNC_XAMCAP
(
6
)
<=
unsigned
(
XAmCap6
);
s_FUNC_XAMCAP
(
7
)
<=
unsigned
(
XAmCap7
);
p_AMmatch
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
mainFSMreset
=
'1'
or
reset
=
'1'
then
AmMatch
<=
(
others
=>
'0'
);
elsif
decode
=
'1'
then
for
i
in
AmMatch
'range
loop
if
DFS_i
(
i
)
=
'1'
then
if
s_FUNC_ADER
(
i
)(
c_ADER_XAM_MODE
)
=
'0'
then
if
unsigned
(
s_FUNC_ADER
(
i
)(
7
downto
2
))
=
unsigned
(
Am
)
then
AmMatch
(
i
)
<=
s_amcap_match
(
i
);
else
AmMatch
(
i
)
<=
'0'
;
end
if
;
else
if
(
unsigned
(
XAm
)
=
unsigned
(
s_FUNC_ADER
(
i
)(
9
downto
2
)))
then
AmMatch
(
i
)
<=
s_xamcap_match
(
i
)
and
s_amcap_match
(
i
);
else
AmMatch
(
i
)
<=
'0'
;
end
if
;
end
if
;
else
if
s_FUNC_ADER
(
i
)(
c_ADER_XAM_MODE
)
=
'1'
then
AmMatch
(
i
)
<=
s_xamcap_match
(
i
)
and
s_amcap_match
(
i
);
else
AmMatch
(
i
)
<=
s_amcap_match
(
i
);
end
if
;
end
if
;
end
loop
;
end
if
;
end
if
;
end
process
;
-- Check if the AM is in the AMCAP register
process
(
s_FUNC_AMCAP
,
Am
)
begin
s_amcap_match
<=
(
others
=>
'0'
);
for
i
in
0
to
7
loop
s_amcap_match
(
i
)
<=
s_FUNC_AMCAP
(
i
)(
to_integer
(
unsigned
(
Am
)));
end
loop
;
end
process
;
-- Check if the XAM is in the XAMCAP register
process
(
s_FUNC_XAMCAP
,
XAm
)
begin
s_xamcap_match
<=
(
others
=>
'0'
);
for
i
in
0
to
7
loop
s_xamcap_match
(
i
)
<=
s_FUNC_XAMCAP
(
i
)(
to_integer
(
unsigned
(
XAm
)));
end
loop
;
end
process
;
end
Behavioral
;
hdl/vme64x-core/rtl/VME_CRAM.vhd
deleted
100644 → 0
View file @
a3b2fde3
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CRAM (VME_CRAM.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: CRAM memory
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
vme64x_pack
.
all
;
entity
VME_CRAM
is
generic
(
g_BEG_CRAM
:
std_logic_vector
(
23
downto
0
);
g_END_CRAM
:
std_logic_vector
(
23
downto
0
)
);
port
(
clk_i
:
in
std_logic
;
we_i
:
in
std_logic
;
addr_i
:
in
std_logic_vector
(
18
downto
2
);
data_i
:
in
std_logic_vector
(
7
downto
0
);
data_o
:
out
std_logic_vector
(
7
downto
0
)
);
end
VME_CRAM
;
architecture
rtl
of
VME_CRAM
is
type
t_cram
is
array
(
f_size
(
g_BEG_CRAM
,
g_END_CRAM
)
-1
downto
0
)
of
std_logic_vector
(
7
downto
0
);
signal
s_cram
:
t_cram
;
signal
s_addr
:
unsigned
(
18
downto
2
);
signal
s_addr_1
:
unsigned
(
18
downto
2
);
begin
s_addr
<=
unsigned
(
addr_i
(
18
downto
2
));
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
we_i
=
'1'
then
s_cram
(
to_integer
(
s_addr
))
<=
data_i
;
end
if
;
s_addr_1
<=
s_addr
;
end
if
;
end
process
;
data_o
<=
s_cram
(
to_integer
(
s_addr_1
));
end
rtl
;
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @
72eff0ad
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
72eff0ad
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/VME_User_CSR.vhd
View file @
72eff0ad
...
@@ -91,43 +91,55 @@ end VME_User_CSR;
...
@@ -91,43 +91,55 @@ end VME_User_CSR;
architecture
rtl
of
VME_User_CSR
is
architecture
rtl
of
VME_User_CSR
is
signal
s_addr
:
unsigned
(
18
downto
2
);
signal
s_irq_vector
:
std_logic_vector
(
7
downto
0
);
signal
s_irq_level
:
std_logic_vector
(
7
downto
0
);
signal
s_endian
:
std_logic_vector
(
7
downto
0
);
signal
s_wb32bits
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_irq_vector
:
std_logic_vector
(
7
downto
0
);
-- Value for unused memory locations
signal
s_reg_irq_level
:
std_logic_vector
(
7
downto
0
);
constant
c_UNUSED
:
std_logic_vector
(
7
downto
0
)
:
=
x"ff"
;
signal
s_reg_endian
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_wb32bits
:
std_logic_vector
(
7
downto
0
);
begin
-- Addresses
constant
c_IRQ_VECTOR
:
integer
:
=
16
#
0002
f
#/
4
;
constant
c_IRQ_LEVEL
:
integer
:
=
16
#
0002
b
#/
4
;
constant
c_ENDIAN
:
integer
:
=
16
#
00023
#/
4
;
constant
c_TIME0_NS
:
integer
:
=
16
#
0001
f
#/
4
;
constant
c_TIME1_NS
:
integer
:
=
16
#
0001
b
#/
4
;
constant
c_TIME2_NS
:
integer
:
=
16
#
00017
#/
4
;
constant
c_TIME3_NS
:
integer
:
=
16
#
00013
#/
4
;
constant
c_TIME4_NS
:
integer
:
=
16
#
0000
f
#/
4
;
constant
c_BYTES0
:
integer
:
=
16
#
0000
b
#/
4
;
constant
c_BYTES1
:
integer
:
=
16
#
00007
#/
4
;
constant
c_WB32BITS
:
integer
:
=
16
#
00003
#/
4
;
s_addr
<=
unsigned
(
addr_i
);
begin
s_
reg_
wb32bits
<=
x"01"
when
g_WB_DATA_WIDTH
=
32
else
x"00"
;
s_wb32bits
<=
x"01"
when
g_WB_DATA_WIDTH
=
32
else
x"00"
;
-- Write
-- Write
process
(
clk_i
)
process
(
clk_i
)
begin
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
s_
reg_irq_vector
<=
x"00"
;
s_
irq_vector
<=
x"00"
;
s_
reg_irq_level
<=
x"00"
;
s_
irq_level
<=
x"00"
;
s_
reg_endian
<=
x"00"
;
s_
endian
<=
x"00"
;
else
else
if
we_i
=
'1'
then
if
we_i
=
'1'
then
case
s_addr
is
case
to_integer
(
unsigned
(
addr_i
))
is
when
c_
ADDR_IRQ_VECTOR
(
18
downto
2
)
=>
s_reg
_irq_vector
<=
data_i
;
when
c_
IRQ_VECTOR
=>
s
_irq_vector
<=
data_i
;
when
c_
ADDR_IRQ_LEVEL
(
18
downto
2
)
=>
s_reg
_irq_level
<=
data_i
;
when
c_
IRQ_LEVEL
=>
s
_irq_level
<=
data_i
;
when
c_
ADDR_ENDIAN
(
18
downto
2
)
=>
s_reg
_endian
<=
data_i
;
when
c_
ENDIAN
=>
s
_endian
<=
data_i
;
when
others
=>
null
;
when
others
=>
null
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
irq_vector_o
<=
s_
reg_
irq_vector
;
irq_vector_o
<=
s_irq_vector
;
irq_level_o
<=
s_
reg_
irq_level
;
irq_level_o
<=
s_irq_level
;
endian_o
<=
s_
reg_
endian
(
2
downto
0
);
endian_o
<=
s_endian
(
2
downto
0
);
-- Read
-- Read
process
(
clk_i
)
process
(
clk_i
)
...
@@ -136,19 +148,19 @@ begin
...
@@ -136,19 +148,19 @@ begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
data_o
<=
x"00"
;
data_o
<=
x"00"
;
else
else
case
s_addr
is
case
to_integer
(
unsigned
(
addr_i
))
is
when
c_
ADDR_IRQ_VECTOR
(
18
downto
2
)
=>
data_o
<=
s_reg
_irq_vector
;
when
c_
IRQ_VECTOR
=>
data_o
<=
s
_irq_vector
;
when
c_
ADDR_IRQ_LEVEL
(
18
downto
2
)
=>
data_o
<=
s_reg
_irq_level
;
when
c_
IRQ_LEVEL
=>
data_o
<=
s
_irq_level
;
when
c_
ADDR_ENDIAN
(
18
downto
2
)
=>
data_o
<=
s_reg
_endian
;
when
c_
ENDIAN
=>
data_o
<=
s
_endian
;
when
c_
ADDR_TIME0_NS
(
18
downto
2
)
=>
data_o
<=
time_i
(
7
downto
0
);
when
c_
TIME0_NS
=>
data_o
<=
time_i
(
7
downto
0
);
when
c_
ADDR_TIME1_NS
(
18
downto
2
)
=>
data_o
<=
time_i
(
15
downto
8
);
when
c_
TIME1_NS
=>
data_o
<=
time_i
(
15
downto
8
);
when
c_
ADDR_TIME2_NS
(
18
downto
2
)
=>
data_o
<=
time_i
(
23
downto
16
);
when
c_
TIME2_NS
=>
data_o
<=
time_i
(
23
downto
16
);
when
c_
ADDR_TIME3_NS
(
18
downto
2
)
=>
data_o
<=
time_i
(
31
downto
24
);
when
c_
TIME3_NS
=>
data_o
<=
time_i
(
31
downto
24
);
when
c_
ADDR_TIME4_NS
(
18
downto
2
)
=>
data_o
<=
time_i
(
39
downto
32
);
when
c_
TIME4_NS
=>
data_o
<=
time_i
(
39
downto
32
);
when
c_
ADDR_BYTES0
(
18
downto
2
)
=>
data_o
<=
bytes_i
(
7
downto
0
);
when
c_
BYTES0
=>
data_o
<=
bytes_i
(
7
downto
0
);
when
c_
ADDR_BYTES1
(
18
downto
2
)
=>
data_o
<=
bytes_i
(
15
downto
8
);
when
c_
BYTES1
=>
data_o
<=
bytes_i
(
15
downto
8
);
when
c_
ADDR_WB32BITS
(
18
downto
2
)
=>
data_o
<=
s_reg
_wb32bits
;
when
c_
WB32BITS
=>
data_o
<=
s
_wb32bits
;
when
others
=>
data_o
<=
x"ff"
;
when
others
=>
data_o
<=
c_UNUSED
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
if
;
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
72eff0ad
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
72eff0ad
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
72eff0ad
...
@@ -142,6 +142,7 @@ entity xvme64x_core is
...
@@ -142,6 +142,7 @@ entity xvme64x_core is
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
...
@@ -275,6 +276,7 @@ begin -- wrapper
...
@@ -275,6 +276,7 @@ begin -- wrapper
STALL_i
=>
master_i
.
stall
,
STALL_i
=>
master_i
.
stall
,
endian_i
=>
endian_i
,
endian_i
=>
endian_i
,
function_o
=>
function_o
,
user_csr_addr_o
=>
user_csr_addr_o
,
user_csr_addr_o
=>
user_csr_addr_o
,
user_csr_data_i
=>
user_csr_data_i
,
user_csr_data_i
=>
user_csr_data_i
,
...
...
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @
72eff0ad
...
@@ -54,7 +54,6 @@ package xvme64x_core_pkg is
...
@@ -54,7 +54,6 @@ package xvme64x_core_pkg is
type
t_vme64x_out
is
record
type
t_vme64x_out
is
record
iackout_n
:
std_logic
;
iackout_n
:
std_logic
;
dtack_oe
:
std_logic
;
dtack_oe
:
std_logic
;
dtack_n
:
std_logic
;
dtack_n
:
std_logic
;
data_dir
:
std_logic
;
data_dir
:
std_logic
;
...
@@ -164,6 +163,7 @@ package xvme64x_core_pkg is
...
@@ -164,6 +163,7 @@ package xvme64x_core_pkg is
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
...
...
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