Maintenance scheduled 24th July -- expect downtime along that day

Commit 73232ebd authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: further cleanup of WB INT and default value for int input when not used

parent a120e226
......@@ -85,7 +85,6 @@ entity vme64x_core is
wb_err_i : std_logic;
wb_rty_i : std_logic;
wb_stall_i : std_logic;
wb_int_i : std_logic;
wb_dat_i : t_wishbone_data;
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
......@@ -183,7 +182,6 @@ begin
wb_i.err => wb_err_i,
wb_i.rty => wb_rty_i,
wb_i.stall => wb_stall_i,
wb_i.int => wb_int_i,
wb_i.dat => wb_dat_i,
wb_o.cyc => wb_cyc_o,
wb_o.stb => wb_stb_o,
......
......@@ -215,7 +215,7 @@ package vme64x_pkg is
wb_i : in t_wishbone_master_in;
wb_o : out t_wishbone_master_out;
int_i : in std_logic;
int_i : in std_logic := '0';
irq_ack_o : out std_logic;
......
......@@ -114,7 +114,7 @@ entity xvme64x_core is
-- Interrupt input from the master side.
-- Previously it was part of the wishbone interface, but is now separate
-- as interrupt is not defined by wishbone.
int_i : in std_logic;
int_i : in std_logic := '0';
-- When the IRQ controller acknowledges the Interrupt cycle it sends a
-- pulse to the IRQ Generator.
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment