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VME64x core
Commits
7c71c06b
Commit
7c71c06b
authored
Oct 24, 2017
by
Tristan Gingold
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Implement g_DECODE_AM (for backward compatibility).
parent
10adb5c6
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7 changed files
with
56 additions
and
14 deletions
+56
-14
VME64x_v2_specs.txt
documentation/specifications/VME64x_v2_specs.txt
+4
-6
VME64xCore_Top.vhd
hdl/rtl/VME64xCore_Top.vhd
+10
-2
VME_Funct_Match.vhd
hdl/rtl/VME_Funct_Match.vhd
+4
-2
VME_bus.vhd
hdl/rtl/VME_bus.vhd
+2
-1
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+2
-0
xvme64x_core_pkg.vhd
hdl/rtl/xvme64x_core_pkg.vhd
+1
-0
top_tb.vhd
hdl/sim/simple_tb/top_tb.vhd
+33
-3
No files found.
documentation/specifications/VME64x_v2_specs.txt
View file @
7c71c06b
...
...
@@ -15,6 +15,10 @@ Features
usage.
* CSR Reset bit is handled as a pulse (will reset on the next write).
This doesn't follow the standard, but is needed for software compatibility.
* When g_DECODE_AM is set to false (non-default), the decoders will use
AMCAP (instead of the ADER.AM field) to check AM. So a decoder will trigger
for all its AMCAP bit. This is for compatibility with previous versions of
the core.
* DTACK/BERR are supposed to be released at most 30ns once DS is released.
The design needs 4 clocks to release them, which means the min frequency
is supposed to 133Mhz
...
...
@@ -89,12 +93,6 @@ In addition to reset and clock, the ports are used for VME and WB signals,
to connect a user defined CSR or CR memory, interrupts from the WB slave,
VME irq level and vector. See port declaration for details.
TODO:
-----
* Stick DFSR and XAM to 0
* Put FF in IOB for all VME lines
VITAL-1 rules
-------------
...
...
hdl/rtl/VME64xCore_Top.vhd
View file @
7c71c06b
...
...
@@ -115,6 +115,12 @@ entity VME64xCore_Top is
g_WB_ADDR_WIDTH
:
integer
:
=
c_ADDR_WIDTH
;
-- WB addr width: <= 32
g_USER_CSR_EXT
:
boolean
:
=
false
;
-- Use external user CSR
-- Consider AM field of ADER to decode addresses. This is what the VME64x
-- standard says. However, for compatibility with previous implementations
-- (or to reduce resources), it is possible for a decoder to allow all AM
-- declared in the AMCAP.
g_DECODE_AM
:
boolean
:
=
true
;
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
...
...
@@ -402,7 +408,8 @@ begin
generic
map
(
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
,
g_DECODE_AM
=>
g_DECODE_AM
)
port
map
(
clk_i
=>
clk_i
,
...
...
@@ -476,7 +483,8 @@ begin
Inst_VME_Funct_Match
:
entity
work
.
VME_Funct_Match
generic
map
(
g_ADEM
=>
c_ADEM
,
g_AMCAP
=>
c_AMCAP
g_AMCAP
=>
c_AMCAP
,
g_DECODE_AM
=>
g_DECODE_AM
)
port
map
(
clk_i
=>
clk_i
,
...
...
hdl/rtl/VME_Funct_Match.vhd
View file @
7c71c06b
...
...
@@ -39,7 +39,8 @@ use work.vme64x_pack.all;
entity
VME_Funct_Match
is
generic
(
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
)
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_DECODE_AM
:
boolean
);
port
(
clk_i
:
in
std_logic
;
...
...
@@ -79,7 +80,8 @@ begin
s_function
(
i
)
<=
'1'
when
(((
addr_i
(
c_ADEM_M
)
and
g_ADEM
(
i
)(
c_ADEM_M
))
=
ader_i
(
i
)(
c_ADEM_M
))
and
(
am_i
=
ader_i
(
i
)(
c_ADER_AM
)))
and
((
am_i
=
ader_i
(
i
)(
c_ADER_AM
))
or
not
g_DECODE_AM
))
else
'0'
;
-- True if the AM part of ADER is enabled by AMCAP
s_ader_am_valid
(
i
)
<=
...
...
hdl/rtl/VME_bus.vhd
View file @
7c71c06b
...
...
@@ -71,7 +71,8 @@ entity VME_bus is
generic
(
g_CLOCK_PERIOD
:
integer
;
g_WB_DATA_WIDTH
:
integer
;
g_WB_ADDR_WIDTH
:
integer
g_WB_ADDR_WIDTH
:
integer
;
g_DECODE_AM
:
boolean
);
port
(
clk_i
:
in
std_logic
;
...
...
hdl/rtl/xvme64x_core.vhd
View file @
7c71c06b
...
...
@@ -40,6 +40,7 @@ entity xvme64x_core is
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_DECODE_AM
:
boolean
:
=
true
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
-- CR/CSR
...
...
@@ -159,6 +160,7 @@ begin -- wrapper
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
,
g_DECODE_AM
=>
g_DECODE_AM
,
g_USER_CSR_EXT
=>
g_USER_CSR_EXT
,
g_MANUFACTURER_ID
=>
g_MANUFACTURER_ID
,
g_BOARD_ID
=>
g_BOARD_ID
,
...
...
hdl/rtl/xvme64x_core_pkg.vhd
View file @
7c71c06b
...
...
@@ -81,6 +81,7 @@ package xvme64x_core_pkg is
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_wishbone_data_width
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_wishbone_address_width
;
g_DECODE_AM
:
boolean
:
=
true
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_SVEC_ID
;
...
...
hdl/sim/simple_tb/top_tb.vhd
View file @
7c71c06b
...
...
@@ -30,7 +30,7 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
entity
top_tb
is
generic
(
g_SCENARIO
:
natural
range
0
to
7
:
=
6
);
generic
(
g_SCENARIO
:
natural
range
0
to
9
:
=
6
);
end
;
library
ieee
;
...
...
@@ -263,10 +263,11 @@ begin
xor
slave_ga
(
1
)
xor
slave_ga
(
0
));
end
block
;
vme64xcore
:
VME64xCore_Top
vme64xcore
:
entity
work
.
VME64xCore_Top
generic
map
(
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
)
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
,
g_DECODE_AM
=>
(
g_SCENARIO
/=
9
))
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
...
...
@@ -1282,6 +1283,35 @@ begin
assert
d16
=
x"8765"
report
"bad read16 with delayed DS"
severity
error
;
when
8
|
9
=>
-- Check AM decoders (8: DECODE_AM = true, 9: DECODE_AM = false)
-- Set ADER
write8_conf
(
x"7_ff63"
,
x"56"
);
write8_conf
(
x"7_ff6f"
,
c_AM_A32
&
"00"
);
read8_conf
(
x"7_ff63"
,
d8
);
assert
d8
=
x"56"
report
"bad ADER0 value"
severity
error
;
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
-- WB read
read8
(
x"56_00_00_00"
,
c_AM_A32
,
d8
);
assert
d8
=
x"00"
report
"bad read at 000"
severity
error
;
-- Try to read with a wrong AM.
read8
(
x"56_00_00_00"
,
c_AM_A32_SUP
,
d8
);
if
g_SCENARIO
=
8
then
assert
d8
=
"XXXXXXXX"
report
"unexpected reply"
severity
error
;
else
assert
d8
=
x"00"
report
"bad read at 000 (no AM decode)"
severity
error
;
end
if
;
-- However, the A24 decoder is not enabled.
read8
(
x"56_00_00_00"
,
c_AM_A24_S
,
d8
);
assert
d8
=
"XXXXXXXX"
report
"unexpected reply"
severity
error
;
-- TODO: check IACK propagation.
end
case
;
...
...
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