vme_cr_csr_space.vhd: minor refactoring.

8b9e164d · Tristan Gingold · 26ae1414 · 8b9e164d
Commit 8b9e164d authored Apr 15, 2020 by Tristan Gingold
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vme_cr_csr_space.vhd hdl/rtl/vme_cr_csr_space.vhd +3 -2

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--- a/hdl/rtl/vme_cr_csr_space.vhd
+++ b/hdl/rtl/vme_cr_csr_space.vhd
@@ -190,11 +190,9 @@ architecture rtl of vme_cr_csr_space is
  -- CRAM
  type t_cram is array (c_CRAM_SIZE-1 downto 0) of std_logic_vector(7 downto 0);

-  signal s_cram             : t_cram;
  signal s_cram_data        : std_logic_vector(7 downto 0);
  signal s_cram_waddr       : unsigned(18 downto 2);
  signal s_cram_raddr       : unsigned(18 downto 2);
-  signal s_cram_we          : std_logic;

  -- Addresses
  subtype crcsr_addr is unsigned(18 downto 2);
@@ -507,6 +505,9 @@ begin
  -- CRAM
  ------------------------------------------------------------------------------
  gen_cram_ena: if c_CRAM_ENA = true generate
+    signal s_cram    : t_cram;
+    signal s_cram_we : std_logic;
+  begin
    s_cram_access <= '1' when s_addr >= c_BEG_CRAM and
                              s_addr <= c_END_CRAM
                         else '0';