Maintenance scheduled 24th July -- expect downtime along that day

Commit a2ee4ac4 authored by Tom Levens's avatar Tom Levens

Normalise case of generics and ports

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent cd83b258
......@@ -11,47 +11,47 @@ use work.vme64x_pkg.all;
entity vme64x_core is
generic (
g_clock_period : natural;
g_decode_am : boolean := true;
g_user_csr_ext : boolean := false;
g_wb_granularity : t_wishbone_address_granularity;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"000000";
g_end_cram : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_decoder_0_adem : std_logic_vector(31 downto 0) := x"ff000000";
g_decoder_0_amcap : std_logic_vector(63 downto 0) := x"00000000_0000ff00";
g_decoder_0_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_1_adem : std_logic_vector(31 downto 0) := x"fff80000";
g_decoder_1_amcap : std_logic_vector(63 downto 0) := x"ff000000_00000000";
g_decoder_1_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_2_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_2_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_2_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_3_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_3_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_3_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_4_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_4_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_4_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_5_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_5_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_5_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_6_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_6_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_6_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_7_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_7_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_7_dawpr : std_logic_vector(7 downto 0) := x"84");
g_CLOCK_PERIOD : natural;
g_DECODE_AM : boolean := true;
g_USER_CSR_EXT : boolean := false;
g_WB_GRANULARITY : t_wishbone_address_granularity;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
g_REVISION_ID : std_logic_vector(31 downto 0);
g_PROGRAM_ID : std_logic_vector(7 downto 0);
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_END_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_DECODER_0_ADEM : std_logic_vector(31 downto 0) := x"ff000000";
g_DECODER_0_AMCAP : std_logic_vector(63 downto 0) := x"00000000_0000ff00";
g_DECODER_0_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_1_ADEM : std_logic_vector(31 downto 0) := x"fff80000";
g_DECODER_1_AMCAP : std_logic_vector(63 downto 0) := x"ff000000_00000000";
g_DECODER_1_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_2_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_2_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_2_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_3_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_3_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_3_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_4_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_4_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_4_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_5_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_5_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_5_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_6_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_6_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_6_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_7_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_7_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_7_DAWPR : std_logic_vector(7 downto 0) := x"84");
port (
clk_i : std_logic;
rst_n_i : std_logic;
......@@ -108,47 +108,47 @@ architecture unwrap of vme64x_core is
begin
inst : entity work.xvme64x_core
generic map (
g_clock_period => g_clock_period,
g_decode_am => g_decode_am,
g_user_csr_ext => g_user_csr_ext,
g_wb_granularity => g_wb_granularity,
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_decoder(0).adem => g_decoder_0_adem,
g_decoder(0).amcap => g_decoder_0_amcap,
g_decoder(0).dawpr => g_decoder_0_dawpr,
g_decoder(1).adem => g_decoder_1_adem,
g_decoder(1).amcap => g_decoder_1_amcap,
g_decoder(1).dawpr => g_decoder_1_dawpr,
g_decoder(2).adem => g_decoder_2_adem,
g_decoder(2).amcap => g_decoder_2_amcap,
g_decoder(2).dawpr => g_decoder_2_dawpr,
g_decoder(3).adem => g_decoder_3_adem,
g_decoder(3).amcap => g_decoder_3_amcap,
g_decoder(3).dawpr => g_decoder_3_dawpr,
g_decoder(4).adem => g_decoder_4_adem,
g_decoder(4).amcap => g_decoder_4_amcap,
g_decoder(4).dawpr => g_decoder_4_dawpr,
g_decoder(5).adem => g_decoder_5_adem,
g_decoder(5).amcap => g_decoder_5_amcap,
g_decoder(5).dawpr => g_decoder_5_dawpr,
g_decoder(6).adem => g_decoder_6_adem,
g_decoder(6).amcap => g_decoder_6_amcap,
g_decoder(6).dawpr => g_decoder_6_dawpr,
g_decoder(7).adem => g_decoder_7_adem,
g_decoder(7).amcap => g_decoder_7_amcap,
g_decoder(7).dawpr => g_decoder_7_dawpr)
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_DECODE_AM => g_DECODE_AM,
g_USER_CSR_EXT => g_USER_CSR_EXT,
g_WB_GRANULARITY => g_WB_GRANULARITY,
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_DECODER(0).adem => g_DECODER_0_ADEM,
g_DECODER(0).amcap => g_DECODER_0_AMCAP,
g_DECODER(0).dawpr => g_DECODER_0_DAWPR,
g_DECODER(1).adem => g_DECODER_1_ADEM,
g_DECODER(1).amcap => g_DECODER_1_AMCAP,
g_DECODER(1).dawpr => g_DECODER_1_DAWPR,
g_DECODER(2).adem => g_DECODER_2_ADEM,
g_DECODER(2).amcap => g_DECODER_2_AMCAP,
g_DECODER(2).dawpr => g_DECODER_2_DAWPR,
g_DECODER(3).adem => g_DECODER_3_ADEM,
g_DECODER(3).amcap => g_DECODER_3_AMCAP,
g_DECODER(3).dawpr => g_DECODER_3_DAWPR,
g_DECODER(4).adem => g_DECODER_4_ADEM,
g_DECODER(4).amcap => g_DECODER_4_AMCAP,
g_DECODER(4).dawpr => g_DECODER_4_DAWPR,
g_DECODER(5).adem => g_DECODER_5_ADEM,
g_DECODER(5).amcap => g_DECODER_5_AMCAP,
g_DECODER(5).dawpr => g_DECODER_5_DAWPR,
g_DECODER(6).adem => g_DECODER_6_ADEM,
g_DECODER(6).amcap => g_DECODER_6_AMCAP,
g_DECODER(6).dawpr => g_DECODER_6_DAWPR,
g_DECODER(7).adem => g_DECODER_7_ADEM,
g_DECODER(7).amcap => g_DECODER_7_AMCAP,
g_DECODER(7).dawpr => g_DECODER_7_DAWPR)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
This diff is collapsed.
......@@ -265,9 +265,9 @@ architecture rtl of vme_cr_csr_space is
cr(16#03d#) := x"0e"; -- Interrupt cap
cr(16#03f#) := x"81"; -- CRAM DAW
for i in 0 to 7 loop
cr(16#040# + i) := g_decoder(i).dawpr;
cr(16#048# + i*8 to 16#04f# + i*8) := f_cr_vec(g_decoder(i).amcap);
cr(16#188# + i*4 to 16#18b# + i*4) := f_cr_vec(g_decoder(i).adem);
cr(16#040# + i) := g_DECODER(i).dawpr;
cr(16#048# + i*8 to 16#04f# + i*8) := f_cr_vec(g_DECODER(i).amcap);
cr(16#188# + i*4 to 16#18b# + i*4) := f_cr_vec(g_DECODER(i).adem);
end loop;
for i in cr'range loop
crc := crc + unsigned(cr(i));
......@@ -432,7 +432,7 @@ begin
-- resources.
gen_ader_o: for i in s_reg_ader'range generate
ader_o (i) <=
s_reg_ader (i) and ((g_decoder(i).adem and c_ADEM_MASK) or c_ADER_MASK);
s_reg_ader (i) and ((g_DECODER(i).adem and c_ADEM_MASK) or c_ADER_MASK);
end generate;
-- Read
......@@ -445,7 +445,7 @@ begin
if idx <= ader_o'high then
v_byte := 3 - to_integer(s_addr(3 downto 2));
ader := s_reg_ader(idx)
and ((g_decoder(idx).adem and c_ADEM_MASK) or c_ADER_MASK);
and ((g_DECODER(idx).adem and c_ADEM_MASK) or c_ADER_MASK);
s_csr_data <= ader(8*v_byte + 7 downto 8*v_byte);
end if;
end Get_ADER;
......
......@@ -72,14 +72,14 @@ begin
gen_match_loop : for i in ader_i'range generate
-- True in case of match
s_function(i) <=
'1' when (((addr_i(t_ADEM_M) and g_decoder(i).adem(t_ADEM_M))
'1' when (((addr_i(t_ADEM_M) and g_DECODER(i).adem(t_ADEM_M))
= ader_i(i)(t_ADEM_M))
and ((am_i = ader_i(i)(t_ADER_AM))
or not g_DECODE_AM))
else '0';
-- True if the AM part of ADER is enabled by AMCAP
s_ader_am_valid(i) <=
g_decoder(i).amcap(to_integer(unsigned(ader_i(i)(t_ADER_AM))));
g_DECODER(i).amcap(to_integer(unsigned(ader_i(i)(t_ADER_AM))));
end generate;
------------------------------------------------------------------------------
......@@ -122,7 +122,7 @@ begin
if s_function_sel_valid = '1' then
mask := (others => '0');
mask(t_ADEM_M) := g_decoder(s_function_sel).adem(t_ADEM_M);
mask(t_ADEM_M) := g_DECODER(s_function_sel).adem(t_ADEM_M);
addr_o <= addr_i and not mask;
decode_sel_o <= '1';
else
......
......@@ -38,14 +38,14 @@ entity vme_irq_controller is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
INT_Level_i : in std_logic_vector (2 downto 0);
INT_Req_i : in std_logic;
int_level_i : in std_logic_vector (2 downto 0);
int_req_i : in std_logic;
-- Set when an irq is pending (not yet acknowledged).
irq_pending_o : out std_logic;
irq_ack_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (7 downto 1)
vme_irq_n_o : out std_logic_vector (7 downto 1)
);
end vme_irq_controller;
......@@ -72,7 +72,7 @@ begin
else
case retry_state is
when WAIT_IRQ =>
if s_irq_pending = '1' and INT_Req_i = '1' then
if s_irq_pending = '1' and int_req_i = '1' then
retry_state <= WAIT_RETRY;
retry_count <= (others => '0');
retry_mask <= '0';
......@@ -81,7 +81,7 @@ begin
end if;
when WAIT_RETRY =>
if INT_Req_i = '0' then
if int_req_i = '0' then
retry_state <= WAIT_IRQ;
else
retry_count <= retry_count + 1;
......@@ -98,27 +98,27 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
VME_IRQ_n_o <= (others => '1');
vme_irq_n_o <= (others => '1');
s_irq_pending <= '0';
else
if s_irq_pending = '0' then
VME_IRQ_n_o <= (others => '1');
vme_irq_n_o <= (others => '1');
if INT_Req_i = '1' and retry_mask = '1' then
if int_req_i = '1' and retry_mask = '1' then
s_irq_pending <= '1';
-- Explicit decoding
case INT_Level_i is
when "001" => VME_IRQ_n_o <= "1111110";
when "010" => VME_IRQ_n_o <= "1111101";
when "011" => VME_IRQ_n_o <= "1111011";
when "100" => VME_IRQ_n_o <= "1110111";
when "101" => VME_IRQ_n_o <= "1101111";
when "110" => VME_IRQ_n_o <= "1011111";
when "111" => VME_IRQ_n_o <= "0111111";
case int_level_i is
when "001" => vme_irq_n_o <= "1111110";
when "010" => vme_irq_n_o <= "1111101";
when "011" => vme_irq_n_o <= "1111011";
when "100" => vme_irq_n_o <= "1110111";
when "101" => vme_irq_n_o <= "1101111";
when "110" => vme_irq_n_o <= "1011111";
when "111" => vme_irq_n_o <= "0111111";
when others =>
-- Incorrect value for INT_Level_i, ignore it.
VME_IRQ_n_o <= "1111111";
-- Incorrect value for int_level_i, ignore it.
vme_irq_n_o <= "1111111";
s_irq_pending <= '0';
end case;
end if;
......
......@@ -43,9 +43,9 @@ entity vme_user_csr is
irq_vector_o : out std_logic_vector( 7 downto 0);
irq_level_o : out std_logic_vector( 2 downto 0)
);
end VME_User_CSR;
end vme_user_csr;
architecture rtl of VME_User_CSR is
architecture rtl of vme_user_csr is
signal s_irq_vector : std_logic_vector(7 downto 0);
signal s_irq_level : std_logic_vector(2 downto 0);
......
......@@ -156,7 +156,7 @@ architecture rtl of xvme64x_core is
signal s_reset_n : std_logic;
signal s_VME_IRQ_n_o : std_logic_vector( 7 downto 1);
signal s_vme_irq_n_o : std_logic_vector( 7 downto 1);
signal s_irq_ack : std_logic;
signal s_irq_pending : std_logic;
......@@ -187,12 +187,12 @@ architecture rtl of xvme64x_core is
signal s_am : std_logic_vector( 5 downto 0);
-- Oversampled input signals
signal s_VME_RST_n : std_logic;
signal s_VME_AS_n : std_logic;
signal s_VME_WRITE_n : std_logic;
signal s_VME_DS_n : std_logic_vector(1 downto 0);
signal s_VME_IACK_n : std_logic;
signal s_VME_IACKIN_n : std_logic;
signal s_vme_rst_n : std_logic;
signal s_vme_as_n : std_logic;
signal s_vme_write_n : std_logic;
signal s_vme_ds_n : std_logic_vector(1 downto 0);
signal s_vme_iack_n : std_logic;
signal s_vme_iackin_n : std_logic;
-- List of supported AM.
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
......@@ -206,8 +206,8 @@ begin
-- Check for invalid bits in ADEM/AMCAP
gen_gchecks: for i in 7 downto 0 generate
constant adem : std_logic_vector(31 downto 0) := g_decoder(i).adem;
constant amcap : std_logic_vector(63 downto 0) := g_decoder(i).amcap;
constant adem : std_logic_vector(31 downto 0) := g_DECODER(i).adem;
constant amcap : std_logic_vector(63 downto 0) := g_DECODER(i).amcap;
begin
assert adem(c_ADEM_FAF) = '0' report "FAF bit set in ADEM"
severity failure;
......@@ -227,7 +227,7 @@ begin
-- necessary to avoid metastability problems, but of course the transfer rate
-- will be slow down a little.
-- NOTE: the reset value is '0', which means that all signals are active
-- at reset. But not for a long time and so is s_VME_RST_n.
-- at reset. But not for a long time and so is s_vme_rst_n.
inst_vme_rst_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_i,
......@@ -272,7 +272,7 @@ begin
port map (clk_i => clk_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_i.iackin_n,
q_o(0) => s_VME_IACKIN_n);
q_o(0) => s_vme_iackin_n);
------------------------------------------------------------------------------
-- VME Bus
......@@ -286,28 +286,28 @@ begin
rst_n_i => s_reset_n,
-- VME
VME_AS_n_i => s_VME_AS_n,
VME_LWORD_n_o => vme_o.lword_n,
VME_LWORD_n_i => vme_i.lword_n,
VME_RETRY_n_o => vme_o.retry_n,
VME_RETRY_OE_o => vme_o.retry_oe,
VME_WRITE_n_i => s_VME_WRITE_n,
VME_DS_n_i => s_VME_DS_n,
VME_DTACK_n_o => vme_o.dtack_n,
VME_DTACK_OE_o => vme_o.dtack_oe,
VME_BERR_n_o => s_vme_berr_n,
VME_ADDR_i => vme_i.addr,
VME_ADDR_o => vme_o.addr,
VME_ADDR_DIR_o => vme_o.addr_dir,
VME_ADDR_OE_N_o => vme_o.addr_oe_n,
VME_DATA_i => vme_i.data,
VME_DATA_o => vme_o.data,
VME_DATA_DIR_o => vme_o.data_dir,
VME_DATA_OE_N_o => vme_o.data_oe_n,
VME_AM_i => vme_i.am,
VME_IACKIN_n_i => s_VME_IACKIN_n,
VME_IACK_n_i => s_VME_IACK_n,
VME_IACKOUT_n_o => vme_o.iackout_n,
vme_as_n_i => s_vme_as_n,
vme_lword_n_o => vme_o.lword_n,
vme_lword_n_i => vme_i.lword_n,
vme_retry_n_o => vme_o.retry_n,
vme_retry_oe_o => vme_o.retry_oe,
vme_write_n_i => s_vme_write_n,
vme_ds_n_i => s_vme_ds_n,
vme_dtack_n_o => vme_o.dtack_n,
vme_dtack_oe_o => vme_o.dtack_oe,
vme_berr_n_o => s_vme_berr_n,
vme_addr_i => vme_i.addr,
vme_addr_o => vme_o.addr,
vme_addr_dir_o => vme_o.addr_dir,
vme_addr_oe_n_o => vme_o.addr_oe_n,
vme_data_i => vme_i.data,
vme_data_o => vme_o.data,
vme_data_dir_o => vme_o.data_dir,
vme_data_oe_n_o => vme_o.data_oe_n,
vme_am_i => vme_i.am,
vme_iackin_n_i => s_vme_iackin_n,
vme_iack_n_i => s_vme_iack_n,
vme_iackout_n_o => vme_o.iackout_n,
-- WB signals
wb_stb_o => wb_o.stb,
......@@ -337,19 +337,19 @@ begin
module_enable_i => s_module_enable,
bar_i => s_bar,
INT_Level_i => s_irq_level,
INT_Vector_i => s_irq_vector,
int_level_i => s_irq_level,
int_vector_i => s_irq_vector,
irq_pending_i => s_irq_pending,
irq_ack_o => s_irq_ack);
s_reset_n <= rst_n_i and s_VME_RST_n;
s_reset_n <= rst_n_i and s_vme_rst_n;
rst_n_o <= s_reset_n and (not s_module_reset);
vme_o.berr_n <= s_vme_berr_n;
inst_vme_funct_match : entity work.vme_funct_match
generic map (
g_decoder => g_decoder,
g_DECODER => g_DECODER,
g_DECODE_AM => g_DECODE_AM
)
port map (
......@@ -380,11 +380,11 @@ begin
port map (
clk_i => clk_i,
rst_n_i => s_reset_n,
INT_Level_i => s_irq_level,
INT_Req_i => int_i,
int_level_i => s_irq_level,
int_req_i => int_i,
irq_pending_o => s_irq_pending,
irq_ack_i => s_irq_ack,
VME_IRQ_n_o => vme_o.irq_n
vme_irq_n_o => vme_o.irq_n
);
------------------------------------------------------------------------------
......@@ -405,7 +405,7 @@ begin
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_decoder => g_decoder
g_DECODER => g_DECODER
)
port map (
clk_i => clk_i,
......
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