Commit a2ee4ac4 authored by Tom Levens's avatar Tom Levens

Normalise case of generics and ports

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent cd83b258
...@@ -11,47 +11,47 @@ use work.vme64x_pkg.all; ...@@ -11,47 +11,47 @@ use work.vme64x_pkg.all;
entity vme64x_core is entity vme64x_core is
generic ( generic (
g_clock_period : natural; g_CLOCK_PERIOD : natural;
g_decode_am : boolean := true; g_DECODE_AM : boolean := true;
g_user_csr_ext : boolean := false; g_USER_CSR_EXT : boolean := false;
g_wb_granularity : t_wishbone_address_granularity; g_WB_GRANULARITY : t_wishbone_address_granularity;
g_manufacturer_id : std_logic_vector(23 downto 0); g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0); g_BOARD_ID : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0); g_REVISION_ID : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0); g_PROGRAM_ID : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000"; g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000"; g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000"; g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"000000"; g_BEG_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_end_cram : std_logic_vector(23 downto 0) := x"000000"; g_END_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33"; g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f"; g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000"; g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_decoder_0_adem : std_logic_vector(31 downto 0) := x"ff000000"; g_DECODER_0_ADEM : std_logic_vector(31 downto 0) := x"ff000000";
g_decoder_0_amcap : std_logic_vector(63 downto 0) := x"00000000_0000ff00"; g_DECODER_0_AMCAP : std_logic_vector(63 downto 0) := x"00000000_0000ff00";
g_decoder_0_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_0_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_1_adem : std_logic_vector(31 downto 0) := x"fff80000"; g_DECODER_1_ADEM : std_logic_vector(31 downto 0) := x"fff80000";
g_decoder_1_amcap : std_logic_vector(63 downto 0) := x"ff000000_00000000"; g_DECODER_1_AMCAP : std_logic_vector(63 downto 0) := x"ff000000_00000000";
g_decoder_1_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_1_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_2_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_2_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_2_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_2_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_2_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_2_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_3_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_3_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_3_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_3_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_3_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_3_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_4_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_4_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_4_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_4_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_4_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_4_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_5_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_5_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_5_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_5_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_5_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_5_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_6_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_6_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_6_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_6_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_6_dawpr : std_logic_vector(7 downto 0) := x"84"; g_DECODER_6_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_decoder_7_adem : std_logic_vector(31 downto 0) := x"00000000"; g_DECODER_7_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_7_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000"; g_DECODER_7_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_7_dawpr : std_logic_vector(7 downto 0) := x"84"); g_DECODER_7_DAWPR : std_logic_vector(7 downto 0) := x"84");
port ( port (
clk_i : std_logic; clk_i : std_logic;
rst_n_i : std_logic; rst_n_i : std_logic;
...@@ -108,47 +108,47 @@ architecture unwrap of vme64x_core is ...@@ -108,47 +108,47 @@ architecture unwrap of vme64x_core is
begin begin
inst : entity work.xvme64x_core inst : entity work.xvme64x_core
generic map ( generic map (
g_clock_period => g_clock_period, g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_decode_am => g_decode_am, g_DECODE_AM => g_DECODE_AM,
g_user_csr_ext => g_user_csr_ext, g_USER_CSR_EXT => g_USER_CSR_EXT,
g_wb_granularity => g_wb_granularity, g_WB_GRANULARITY => g_WB_GRANULARITY,
g_manufacturer_id => g_manufacturer_id, g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_board_id => g_board_id, g_BOARD_ID => g_BOARD_ID,
g_revision_id => g_revision_id, g_REVISION_ID => g_REVISION_ID,
g_program_id => g_program_id, g_PROGRAM_ID => g_PROGRAM_ID,
g_ascii_ptr => g_ascii_ptr, g_ASCII_PTR => g_ASCII_PTR,
g_beg_user_cr => g_beg_user_cr, g_BEG_USER_CR => g_BEG_USER_CR,
g_end_user_cr => g_end_user_cr, g_END_USER_CR => g_END_USER_CR,
g_beg_cram => g_beg_cram, g_BEG_CRAM => g_BEG_CRAM,
g_end_cram => g_end_cram, g_END_CRAM => g_END_CRAM,
g_beg_user_csr => g_beg_user_csr, g_BEG_USER_CSR => g_BEG_USER_CSR,
g_end_user_csr => g_end_user_csr, g_END_USER_CSR => g_END_USER_CSR,
g_beg_sn => g_beg_sn, g_BEG_SN => g_BEG_SN,
g_end_sn => g_end_sn, g_END_SN => g_END_SN,
g_decoder(0).adem => g_decoder_0_adem, g_DECODER(0).adem => g_DECODER_0_ADEM,
g_decoder(0).amcap => g_decoder_0_amcap, g_DECODER(0).amcap => g_DECODER_0_AMCAP,
g_decoder(0).dawpr => g_decoder_0_dawpr, g_DECODER(0).dawpr => g_DECODER_0_DAWPR,
g_decoder(1).adem => g_decoder_1_adem, g_DECODER(1).adem => g_DECODER_1_ADEM,
g_decoder(1).amcap => g_decoder_1_amcap, g_DECODER(1).amcap => g_DECODER_1_AMCAP,
g_decoder(1).dawpr => g_decoder_1_dawpr, g_DECODER(1).dawpr => g_DECODER_1_DAWPR,
g_decoder(2).adem => g_decoder_2_adem, g_DECODER(2).adem => g_DECODER_2_ADEM,
g_decoder(2).amcap => g_decoder_2_amcap, g_DECODER(2).amcap => g_DECODER_2_AMCAP,
g_decoder(2).dawpr => g_decoder_2_dawpr, g_DECODER(2).dawpr => g_DECODER_2_DAWPR,
g_decoder(3).adem => g_decoder_3_adem, g_DECODER(3).adem => g_DECODER_3_ADEM,
g_decoder(3).amcap => g_decoder_3_amcap, g_DECODER(3).amcap => g_DECODER_3_AMCAP,
g_decoder(3).dawpr => g_decoder_3_dawpr, g_DECODER(3).dawpr => g_DECODER_3_DAWPR,
g_decoder(4).adem => g_decoder_4_adem, g_DECODER(4).adem => g_DECODER_4_ADEM,
g_decoder(4).amcap => g_decoder_4_amcap, g_DECODER(4).amcap => g_DECODER_4_AMCAP,
g_decoder(4).dawpr => g_decoder_4_dawpr, g_DECODER(4).dawpr => g_DECODER_4_DAWPR,
g_decoder(5).adem => g_decoder_5_adem, g_DECODER(5).adem => g_DECODER_5_ADEM,
g_decoder(5).amcap => g_decoder_5_amcap, g_DECODER(5).amcap => g_DECODER_5_AMCAP,
g_decoder(5).dawpr => g_decoder_5_dawpr, g_DECODER(5).dawpr => g_DECODER_5_DAWPR,
g_decoder(6).adem => g_decoder_6_adem, g_DECODER(6).adem => g_DECODER_6_ADEM,
g_decoder(6).amcap => g_decoder_6_amcap, g_DECODER(6).amcap => g_DECODER_6_AMCAP,
g_decoder(6).dawpr => g_decoder_6_dawpr, g_DECODER(6).dawpr => g_DECODER_6_DAWPR,
g_decoder(7).adem => g_decoder_7_adem, g_DECODER(7).adem => g_DECODER_7_ADEM,
g_decoder(7).amcap => g_decoder_7_amcap, g_DECODER(7).amcap => g_DECODER_7_AMCAP,
g_decoder(7).dawpr => g_decoder_7_dawpr) g_DECODER(7).dawpr => g_DECODER_7_DAWPR)
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
......
...@@ -41,28 +41,28 @@ entity vme_bus is ...@@ -41,28 +41,28 @@ entity vme_bus is
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- VME signals -- VME signals
VME_AS_n_i : in std_logic; vme_as_n_i : in std_logic;
VME_LWORD_n_o : out std_logic := '0'; vme_lword_n_o : out std_logic := '0';
VME_LWORD_n_i : in std_logic; vme_lword_n_i : in std_logic;
VME_RETRY_n_o : out std_logic; vme_retry_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic; vme_retry_oe_o : out std_logic;
VME_WRITE_n_i : in std_logic; vme_write_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0); vme_ds_n_i : in std_logic_vector(1 downto 0);
VME_DTACK_n_o : out std_logic; vme_dtack_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic; vme_dtack_oe_o : out std_logic;
VME_BERR_n_o : out std_logic; vme_berr_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1); vme_addr_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1) := (others => '0'); vme_addr_o : out std_logic_vector(31 downto 1) := (others => '0');
VME_ADDR_DIR_o : out std_logic; vme_addr_dir_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic; vme_addr_oe_n_o : out std_logic;
VME_DATA_i : in std_logic_vector(31 downto 0); vme_data_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0) := (others => '0'); vme_data_o : out std_logic_vector(31 downto 0) := (others => '0');
VME_DATA_DIR_o : out std_logic; vme_data_dir_o : out std_logic;
VME_DATA_OE_N_o : out std_logic; vme_data_oe_n_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0); vme_am_i : in std_logic_vector(5 downto 0);
VME_IACKIN_n_i : in std_logic; vme_iackin_n_i : in std_logic;
VME_IACK_n_i : in std_logic; vme_iack_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic; vme_iackout_n_o : out std_logic;
-- WB signals -- WB signals
wb_stb_o : out std_logic; wb_stb_o : out std_logic;
...@@ -93,8 +93,8 @@ entity vme_bus is ...@@ -93,8 +93,8 @@ entity vme_bus is
bar_i : in std_logic_vector( 4 downto 0); bar_i : in std_logic_vector( 4 downto 0);
-- Interrupts -- Interrupts
INT_Level_i : in std_logic_vector( 2 downto 0); int_level_i : in std_logic_vector( 2 downto 0);
INT_Vector_i : in std_logic_vector( 7 downto 0); int_vector_i : in std_logic_vector( 7 downto 0);
irq_pending_i : in std_logic; irq_pending_i : in std_logic;
irq_ack_o : out std_logic irq_ack_o : out std_logic
); );
...@@ -138,7 +138,7 @@ architecture rtl of vme_bus is ...@@ -138,7 +138,7 @@ architecture rtl of vme_bus is
TFR_ERROR TFR_ERROR
); );
-- Addressing type (depending on VME_AM_i) -- Addressing type (depending on vme_am_i)
signal s_addressingType : t_addressingType; signal s_addressingType : t_addressingType;
signal s_transferType : t_transferType; signal s_transferType : t_transferType;
...@@ -215,8 +215,8 @@ begin ...@@ -215,8 +215,8 @@ begin
-- L | L | B to A L | L | B to Y -- L | L | B to A L | L | B to Y
-- H | L |A to B, B to Y | -- H | L |A to B, B to Y |
VME_DATA_OE_N_o <= '0'; -- Driven IFF DIR = 1 vme_data_oe_n_o <= '0'; -- Driven IFF DIR = 1
VME_ADDR_OE_N_o <= '0'; -- Driven IFF DIR = 1 vme_addr_oe_n_o <= '0'; -- Driven IFF DIR = 1
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Access Mode Decoders -- Access Mode Decoders
...@@ -263,7 +263,7 @@ begin ...@@ -263,7 +263,7 @@ begin
variable addr_word_incr : natural range 0 to 7; variable addr_word_incr : natural range 0 to 7;
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' or VME_AS_n_i = '1' then if rst_n_i = '0' or vme_as_n_i = '1' then
-- FSM reset after power up, -- FSM reset after power up,
-- software reset, manually reset, -- software reset, manually reset,
-- on rising edge of AS. -- on rising edge of AS.
...@@ -271,15 +271,15 @@ begin ...@@ -271,15 +271,15 @@ begin
decode_start_o <= '0'; decode_start_o <= '0';
-- VME -- VME
VME_DTACK_OE_o <= '0'; vme_dtack_oe_o <= '0';
VME_DTACK_n_o <= '1'; vme_dtack_n_o <= '1';
VME_DATA_DIR_o <= '0'; vme_data_dir_o <= '0';
VME_ADDR_DIR_o <= '0'; vme_addr_dir_o <= '0';
VME_BERR_n_o <= '1'; vme_berr_n_o <= '1';
VME_ADDR_o <= (others => '0'); vme_addr_o <= (others => '0');
VME_LWORD_n_o <= '1'; vme_lword_n_o <= '1';
VME_DATA_o <= (others => '0'); vme_data_o <= (others => '0');
VME_IACKOUT_n_o <= '1'; vme_iackout_n_o <= '1';
s_dataPhase <= '0'; s_dataPhase <= '0';
s_MBLT_Data <= '0'; s_MBLT_Data <= '0';
s_mainFSMstate <= IDLE; s_mainFSMstate <= IDLE;
...@@ -303,27 +303,27 @@ begin ...@@ -303,27 +303,27 @@ begin
else else
s_conf_req <= '0'; s_conf_req <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
VME_DTACK_OE_o <= '0'; vme_dtack_oe_o <= '0';
VME_DTACK_n_o <= '1'; vme_dtack_n_o <= '1';
VME_DATA_DIR_o <= '0'; vme_data_dir_o <= '0';
VME_ADDR_DIR_o <= '0'; vme_addr_dir_o <= '0';
VME_BERR_n_o <= '1'; vme_berr_n_o <= '1';
VME_IACKOUT_n_o <= '1'; vme_iackout_n_o <= '1';
irq_ack_o <= '0'; irq_ack_o <= '0';
case s_mainFSMstate is case s_mainFSMstate is
when IDLE => when IDLE =>
-- Can only be here if VME_AS_n_i has fallen to 0, which starts a -- Can only be here if vme_as_n_i has fallen to 0, which starts a
-- cycle. -- cycle.
assert VME_AS_n_i = '0'; assert vme_as_n_i = '0';
-- Store ADDR, AM and LWORD -- Store ADDR, AM and LWORD
s_ADDRlatched <= VME_ADDR_i; s_ADDRlatched <= vme_addr_i;
s_LWORDlatched_n <= VME_LWORD_n_i; s_LWORDlatched_n <= vme_lword_n_i;
s_AMlatched <= VME_AM_i; s_AMlatched <= vme_am_i;
if VME_IACK_n_i = '1' then if vme_iack_n_i = '1' then
-- VITA-1 Rule 2.11 -- VITA-1 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low. -- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS; s_mainFSMstate <= REFORMAT_ADDRESS;
...@@ -380,8 +380,8 @@ begin ...@@ -380,8 +380,8 @@ begin
-- Check if this slave board is addressed. -- Check if this slave board is addressed.
-- Wait for DS in parallel. -- Wait for DS in parallel.
if VME_DS_n_i /= "11" then if vme_ds_n_i /= "11" then
s_WRITElatched_n <= VME_WRITE_n_i; s_WRITElatched_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1; s_DS_latch_count <= s_DS_latch_count - 1;
end if; end if;
...@@ -394,14 +394,14 @@ begin ...@@ -394,14 +394,14 @@ begin
-- Keep only the local part of the address. -- Keep only the local part of the address.
s_vme_addr_reg <= addr_decoder_i; s_vme_addr_reg <= addr_decoder_i;
if VME_DS_n_i = "11" then if vme_ds_n_i = "11" then
s_mainFSMstate <= WAIT_FOR_DS; s_mainFSMstate <= WAIT_FOR_DS;
else else
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= LATCH_DS;
end if; end if;
else else
-- Another board will answer; wait here the rising edge on -- Another board will answer; wait here the rising edge on
-- VME_AS_i (done by top if). -- vme_as_i (done by top if).
s_mainFSMstate <= WAIT_END; s_mainFSMstate <= WAIT_END;
end if; end if;
else else
...@@ -413,10 +413,10 @@ begin ...@@ -413,10 +413,10 @@ begin
-- wait until DS /= "11" -- wait until DS /= "11"
-- Note: before entering this state, s_DS_latch_count must be set. -- Note: before entering this state, s_DS_latch_count must be set.
if VME_DS_n_i /= "11" then if vme_ds_n_i /= "11" then
-- VITAL-1 Table 4-1 -- VITAL-1 Table 4-1
-- For interrupts ack, the handler MUST NOT drive WRITE* low -- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= VME_WRITE_n_i; s_WRITElatched_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1; s_DS_latch_count <= s_DS_latch_count - 1;
end if; end if;
...@@ -432,8 +432,8 @@ begin ...@@ -432,8 +432,8 @@ begin
-- VITA-1 Rule 2.53a -- VITA-1 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT -- During all read cycles [...], the responding slave MUST NOT
-- drive the D[] lines until DSA* goes low. -- drive the D[] lines until DSA* goes low.
VME_DATA_DIR_o <= s_WRITElatched_n; vme_data_dir_o <= s_WRITElatched_n;
VME_ADDR_DIR_o <= '0'; vme_addr_dir_o <= '0';
if s_transferType = MBLT then if s_transferType = MBLT then
s_dataPhase <= '1'; s_dataPhase <= '1';
...@@ -456,23 +456,23 @@ begin ...@@ -456,23 +456,23 @@ begin
end if; end if;
-- Read DS (which is delayed to avoid metastability). -- Read DS (which is delayed to avoid metastability).
s_DSlatched_n <= VME_DS_n_i; s_DSlatched_n <= vme_ds_n_i;
-- Read DATA (which are stable) -- Read DATA (which are stable)
s_locDataIn(63 downto 33) <= VME_ADDR_i; s_locDataIn(63 downto 33) <= vme_addr_i;
s_LWORDlatched_n <= VME_LWORD_n_i; s_LWORDlatched_n <= vme_lword_n_i;
s_vme_data_reg <= VME_DATA_i; s_vme_data_reg <= vme_data_i;
else else
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= LATCH_DS;
s_DS_latch_count <= s_DS_latch_count - 1; s_DS_latch_count <= s_DS_latch_count - 1;
end if; end if;
when CHECK_TRANSFER_TYPE => when CHECK_TRANSFER_TYPE =>
VME_DATA_DIR_o <= s_WRITElatched_n; vme_data_dir_o <= s_WRITElatched_n;
VME_ADDR_DIR_o <= '0'; vme_addr_dir_o <= '0';
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
-- VME_ADDR is an output during MBLT *read* data transfer. -- vme_addr is an output during MBLT *read* data transfer.
if s_transferType = MBLT and s_WRITElatched_n = '1' then if s_transferType = MBLT and s_WRITElatched_n = '1' then
s_vme_addr_dir <= '1'; s_vme_addr_dir <= '1';
else else
...@@ -521,9 +521,9 @@ begin ...@@ -521,9 +521,9 @@ begin
when MEMORY_REQ => when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to -- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_conf_req signal -- generate a pulse on s_conf_req signal
VME_DTACK_OE_o <= '1'; vme_dtack_oe_o <= '1';
VME_DATA_DIR_o <= s_WRITElatched_n; vme_data_dir_o <= s_WRITElatched_n;
VME_ADDR_DIR_o <= s_vme_addr_dir; vme_addr_dir_o <= s_vme_addr_dir;
-- Assert STB if stall was asserted. -- Assert STB if stall was asserted.
wb_stb_o <= s_card_sel and wb_stall_i; wb_stb_o <= s_card_sel and wb_stall_i;
...@@ -596,13 +596,13 @@ begin ...@@ -596,13 +596,13 @@ begin
end if; end if;
when DATA_TO_BUS => when DATA_TO_BUS =>
VME_DTACK_OE_o <= '1'; vme_dtack_oe_o <= '1';
VME_DATA_DIR_o <= s_WRITElatched_n; vme_data_dir_o <= s_WRITElatched_n;
VME_ADDR_DIR_o <= s_vme_addr_dir; vme_addr_dir_o <= s_vme_addr_dir;
VME_ADDR_o <= s_locDataOut(63 downto 33); vme_addr_o <= s_locDataOut(63 downto 33);
VME_LWORD_n_o <= s_locDataOut(32); vme_lword_n_o <= s_locDataOut(32);
VME_DATA_o <= s_locDataOut(31 downto 0); vme_data_o <= s_locDataOut(31 downto 0);
-- VITA-1 Rule 2.54a -- VITA-1 Rule 2.54a
-- During all read cycles, the responding Slave MUST NOT drive -- During all read cycles, the responding Slave MUST NOT drive
...@@ -610,27 +610,27 @@ begin ...@@ -610,27 +610,27 @@ begin
s_mainFSMstate <= DTACK_LOW; s_mainFSMstate <= DTACK_LOW;
when DTACK_LOW => when DTACK_LOW =>
VME_DTACK_OE_o <= '1'; vme_dtack_oe_o <= '1';
VME_DATA_DIR_o <= s_WRITElatched_n; vme_data_dir_o <= s_WRITElatched_n;
VME_ADDR_DIR_o <= s_vme_addr_dir; vme_addr_dir_o <= s_vme_addr_dir;
-- Set DTACK (or retry or berr) -- Set DTACK (or retry or berr)
if s_card_sel = '1' and s_err = '1' then if s_card_sel = '1' and s_err = '1' then
VME_BERR_n_o <= '0'; vme_berr_n_o <= '0';
else else
VME_DTACK_n_o <= '0'; vme_dtack_n_o <= '0';
end if; end if;
-- VITA-1 Rule 2.57 -- VITA-1 Rule 2.57
-- Once the responding Slave has driven DTACK* or BERR* low, it -- Once the responding Slave has driven DTACK* or BERR* low, it
-- MUST NOT release them or drive DTACK* high until it detects -- MUST NOT release them or drive DTACK* high until it detects
-- both DS0* and DS1* high. -- both DS0* and DS1* high.
if VME_DS_n_i = "11" then if vme_ds_n_i = "11" then
VME_DATA_DIR_o <= '0'; vme_data_dir_o <= '0';
VME_BERR_n_o <= '1'; vme_berr_n_o <= '1';
-- Rescind DTACK. -- Rescind DTACK.
VME_DTACK_n_o <= '1'; vme_dtack_n_o <= '1';
-- DS latch counter -- DS latch counter
s_DS_latch_count <= to_unsigned (c_num_latchDS, 3); s_DS_latch_count <= to_unsigned (c_num_latchDS, 3);
...@@ -656,8 +656,8 @@ begin ...@@ -656,8 +656,8 @@ begin
end if; end if;
when INCREMENT_ADDR => when INCREMENT_ADDR =>
VME_DTACK_OE_o <= '1'; vme_dtack_oe_o <= '1';
VME_ADDR_DIR_o <= s_vme_addr_dir; vme_addr_dir_o <= s_vme_addr_dir;
if s_vme_lword_n_reg = '0' then if s_vme_lword_n_reg = '0' then
if s_transferType = MBLT then if s_transferType = MBLT then
...@@ -683,20 +683,20 @@ begin ...@@ -683,20 +683,20 @@ begin
s_mainFSMstate <= WAIT_FOR_DS; s_mainFSMstate <= WAIT_FOR_DS;
when IRQ_CHECK => when IRQ_CHECK =>
if VME_IACKIN_n_i = '0' then if vme_iackin_n_i = '0' then
if s_ADDRlatched(3 downto 1) = INT_Level_i if s_ADDRlatched(3 downto 1) = int_level_i
and irq_pending_i = '1' and irq_pending_i = '1'
then then
-- That's for us -- That's for us
s_locDataOut <= (others => '0'); s_locDataOut <= (others => '0');
s_locDataOut (7 downto 0) <= INT_Vector_i; s_locDataOut (7 downto 0) <= int_vector_i;
s_irq_sel <= '1'; s_irq_sel <= '1';
irq_ack_o <= '1'; irq_ack_o <= '1';
s_mainFSMstate <= WAIT_FOR_DS; s_mainFSMstate <= WAIT_FOR_DS;
else else
-- Pass -- Pass
VME_IACKOUT_n_o <= '0'; vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS; s_mainFSMstate <= IRQ_PASS;
end if; end if;
else else
...@@ -705,7 +705,7 @@ begin ...@@ -705,7 +705,7 @@ begin
when IRQ_PASS => when IRQ_PASS =>
-- Will stay here until AS is released. -- Will stay here until AS is released.
VME_IACKOUT_n_o <= '0'; vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS; s_mainFSMstate <= IRQ_PASS;
when WAIT_END => when WAIT_END =>
...@@ -722,8 +722,8 @@ begin ...@@ -722,8 +722,8 @@ begin
end process; end process;
-- Retry is not supported -- Retry is not supported
VME_RETRY_n_o <= '1'; vme_retry_n_o <= '1';
VME_RETRY_OE_o <= '0'; vme_retry_oe_o <= '0';
-- WB Master -- WB Master
with g_WB_GRANULARITY select with g_WB_GRANULARITY select
......
...@@ -265,9 +265,9 @@ architecture rtl of vme_cr_csr_space is ...@@ -265,9 +265,9 @@ architecture rtl of vme_cr_csr_space is
cr(16#03d#) := x"0e"; -- Interrupt cap cr(16#03d#) := x"0e"; -- Interrupt cap
cr(16#03f#) := x"81"; -- CRAM DAW cr(16#03f#) := x"81"; -- CRAM DAW
for i in 0 to 7 loop for i in 0 to 7 loop
cr(16#040# + i) := g_decoder(i).dawpr; cr(16#040# + i) := g_DECODER(i).dawpr;
cr(16#048# + i*8 to 16#04f# + i*8) := f_cr_vec(g_decoder(i).amcap); cr(16#048# + i*8 to 16#04f# + i*8) := f_cr_vec(g_DECODER(i).amcap);
cr(16#188# + i*4 to 16#18b# + i*4) := f_cr_vec(g_decoder(i).adem); cr(16#188# + i*4 to 16#18b# + i*4) := f_cr_vec(g_DECODER(i).adem);
end loop; end loop;
for i in cr'range loop for i in cr'range loop
crc := crc + unsigned(cr(i)); crc := crc + unsigned(cr(i));
...@@ -432,7 +432,7 @@ begin ...@@ -432,7 +432,7 @@ begin
-- resources. -- resources.
gen_ader_o: for i in s_reg_ader'range generate gen_ader_o: for i in s_reg_ader'range generate
ader_o (i) <= ader_o (i) <=
s_reg_ader (i) and ((g_decoder(i).adem and c_ADEM_MASK) or c_ADER_MASK); s_reg_ader (i) and ((g_DECODER(i).adem and c_ADEM_MASK) or c_ADER_MASK);
end generate; end generate;
-- Read -- Read
...@@ -445,7 +445,7 @@ begin ...@@ -445,7 +445,7 @@ begin
if idx <= ader_o'high then if idx <= ader_o'high then
v_byte := 3 - to_integer(s_addr(3 downto 2)); v_byte := 3 - to_integer(s_addr(3 downto 2));
ader := s_reg_ader(idx) ader := s_reg_ader(idx)
and ((g_decoder(idx).adem and c_ADEM_MASK) or c_ADER_MASK); and ((g_DECODER(idx).adem and c_ADEM_MASK) or c_ADER_MASK);
s_csr_data <= ader(8*v_byte + 7 downto 8*v_byte); s_csr_data <= ader(8*v_byte + 7 downto 8*v_byte);
end if; end if;
end Get_ADER; end Get_ADER;
......
...@@ -72,14 +72,14 @@ begin ...@@ -72,14 +72,14 @@ begin
gen_match_loop : for i in ader_i'range generate gen_match_loop : for i in ader_i'range generate
-- True in case of match -- True in case of match
s_function(i) <= s_function(i) <=
'1' when (((addr_i(t_ADEM_M) and g_decoder(i).adem(t_ADEM_M)) '1' when (((addr_i(t_ADEM_M) and g_DECODER(i).adem(t_ADEM_M))
= ader_i(i)(t_ADEM_M)) = ader_i(i)(t_ADEM_M))
and ((am_i = ader_i(i)(t_ADER_AM)) and ((am_i = ader_i(i)(t_ADER_AM))
or not g_DECODE_AM)) or not g_DECODE_AM))
else '0'; else '0';
-- True if the AM part of ADER is enabled by AMCAP -- True if the AM part of ADER is enabled by AMCAP
s_ader_am_valid(i) <= s_ader_am_valid(i) <=
g_decoder(i).amcap(to_integer(unsigned(ader_i(i)(t_ADER_AM)))); g_DECODER(i).amcap(to_integer(unsigned(ader_i(i)(t_ADER_AM))));
end generate; end generate;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -122,7 +122,7 @@ begin ...@@ -122,7 +122,7 @@ begin
if s_function_sel_valid = '1' then if s_function_sel_valid = '1' then
mask := (others => '0'); mask := (others => '0');
mask(t_ADEM_M) := g_decoder(s_function_sel).adem(t_ADEM_M); mask(t_ADEM_M) := g_DECODER(s_function_sel).adem(t_ADEM_M);
addr_o <= addr_i and not mask; addr_o <= addr_i and not mask;
decode_sel_o <= '1'; decode_sel_o <= '1';
else else
......
...@@ -38,14 +38,14 @@ entity vme_irq_controller is ...@@ -38,14 +38,14 @@ entity vme_irq_controller is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
INT_Level_i : in std_logic_vector (2 downto 0); int_level_i : in std_logic_vector (2 downto 0);
INT_Req_i : in std_logic; int_req_i : in std_logic;
-- Set when an irq is pending (not yet acknowledged). -- Set when an irq is pending (not yet acknowledged).
irq_pending_o : out std_logic; irq_pending_o : out std_logic;
irq_ack_i : in std_logic; irq_ack_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (7 downto 1) vme_irq_n_o : out std_logic_vector (7 downto 1)
); );
end vme_irq_controller; end vme_irq_controller;
...@@ -72,7 +72,7 @@ begin ...@@ -72,7 +72,7 @@ begin
else else
case retry_state is case retry_state is
when WAIT_IRQ => when WAIT_IRQ =>
if s_irq_pending = '1' and INT_Req_i = '1' then if s_irq_pending = '1' and int_req_i = '1' then
retry_state <= WAIT_RETRY; retry_state <= WAIT_RETRY;
retry_count <= (others => '0'); retry_count <= (others => '0');
retry_mask <= '0'; retry_mask <= '0';
...@@ -81,7 +81,7 @@ begin ...@@ -81,7 +81,7 @@ begin
end if; end if;
when WAIT_RETRY => when WAIT_RETRY =>
if INT_Req_i = '0' then if int_req_i = '0' then
retry_state <= WAIT_IRQ; retry_state <= WAIT_IRQ;
else else
retry_count <= retry_count + 1; retry_count <= retry_count + 1;
...@@ -98,27 +98,27 @@ begin ...@@ -98,27 +98,27 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
VME_IRQ_n_o <= (others => '1'); vme_irq_n_o <= (others => '1');
s_irq_pending <= '0'; s_irq_pending <= '0';
else else
if s_irq_pending = '0' then if s_irq_pending = '0' then
VME_IRQ_n_o <= (others => '1'); vme_irq_n_o <= (others => '1');
if INT_Req_i = '1' and retry_mask = '1' then if int_req_i = '1' and retry_mask = '1' then
s_irq_pending <= '1'; s_irq_pending <= '1';
-- Explicit decoding -- Explicit decoding
case INT_Level_i is case int_level_i is
when "001" => VME_IRQ_n_o <= "1111110"; when "001" => vme_irq_n_o <= "1111110";
when "010" => VME_IRQ_n_o <= "1111101"; when "010" => vme_irq_n_o <= "1111101";
when "011" => VME_IRQ_n_o <= "1111011"; when "011" => vme_irq_n_o <= "1111011";
when "100" => VME_IRQ_n_o <= "1110111"; when "100" => vme_irq_n_o <= "1110111";
when "101" => VME_IRQ_n_o <= "1101111"; when "101" => vme_irq_n_o <= "1101111";
when "110" => VME_IRQ_n_o <= "1011111"; when "110" => vme_irq_n_o <= "1011111";
when "111" => VME_IRQ_n_o <= "0111111"; when "111" => vme_irq_n_o <= "0111111";
when others => when others =>
-- Incorrect value for INT_Level_i, ignore it. -- Incorrect value for int_level_i, ignore it.
VME_IRQ_n_o <= "1111111"; vme_irq_n_o <= "1111111";
s_irq_pending <= '0'; s_irq_pending <= '0';
end case; end case;
end if; end if;
......
...@@ -43,9 +43,9 @@ entity vme_user_csr is ...@@ -43,9 +43,9 @@ entity vme_user_csr is
irq_vector_o : out std_logic_vector( 7 downto 0); irq_vector_o : out std_logic_vector( 7 downto 0);
irq_level_o : out std_logic_vector( 2 downto 0) irq_level_o : out std_logic_vector( 2 downto 0)
); );
end VME_User_CSR; end vme_user_csr;
architecture rtl of VME_User_CSR is architecture rtl of vme_user_csr is
signal s_irq_vector : std_logic_vector(7 downto 0); signal s_irq_vector : std_logic_vector(7 downto 0);
signal s_irq_level : std_logic_vector(2 downto 0); signal s_irq_level : std_logic_vector(2 downto 0);
......
...@@ -156,7 +156,7 @@ architecture rtl of xvme64x_core is ...@@ -156,7 +156,7 @@ architecture rtl of xvme64x_core is
signal s_reset_n : std_logic; signal s_reset_n : std_logic;
signal s_VME_IRQ_n_o : std_logic_vector( 7 downto 1); signal s_vme_irq_n_o : std_logic_vector( 7 downto 1);
signal s_irq_ack : std_logic; signal s_irq_ack : std_logic;
signal s_irq_pending : std_logic; signal s_irq_pending : std_logic;
...@@ -187,12 +187,12 @@ architecture rtl of xvme64x_core is ...@@ -187,12 +187,12 @@ architecture rtl of xvme64x_core is
signal s_am : std_logic_vector( 5 downto 0); signal s_am : std_logic_vector( 5 downto 0);
-- Oversampled input signals -- Oversampled input signals
signal s_VME_RST_n : std_logic; signal s_vme_rst_n : std_logic;
signal s_VME_AS_n : std_logic; signal s_vme_as_n : std_logic;
signal s_VME_WRITE_n : std_logic; signal s_vme_write_n : std_logic;
signal s_VME_DS_n : std_logic_vector(1 downto 0); signal s_vme_ds_n : std_logic_vector(1 downto 0);
signal s_VME_IACK_n : std_logic; signal s_vme_iack_n : std_logic;
signal s_VME_IACKIN_n : std_logic; signal s_vme_iackin_n : std_logic;
-- List of supported AM. -- List of supported AM.
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) := constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
...@@ -206,8 +206,8 @@ begin ...@@ -206,8 +206,8 @@ begin
-- Check for invalid bits in ADEM/AMCAP -- Check for invalid bits in ADEM/AMCAP
gen_gchecks: for i in 7 downto 0 generate gen_gchecks: for i in 7 downto 0 generate
constant adem : std_logic_vector(31 downto 0) := g_decoder(i).adem; constant adem : std_logic_vector(31 downto 0) := g_DECODER(i).adem;
constant amcap : std_logic_vector(63 downto 0) := g_decoder(i).amcap; constant amcap : std_logic_vector(63 downto 0) := g_DECODER(i).amcap;
begin begin
assert adem(c_ADEM_FAF) = '0' report "FAF bit set in ADEM" assert adem(c_ADEM_FAF) = '0' report "FAF bit set in ADEM"
severity failure; severity failure;
...@@ -227,7 +227,7 @@ begin ...@@ -227,7 +227,7 @@ begin
-- necessary to avoid metastability problems, but of course the transfer rate -- necessary to avoid metastability problems, but of course the transfer rate
-- will be slow down a little. -- will be slow down a little.
-- NOTE: the reset value is '0', which means that all signals are active -- NOTE: the reset value is '0', which means that all signals are active
-- at reset. But not for a long time and so is s_VME_RST_n. -- at reset. But not for a long time and so is s_vme_rst_n.
inst_vme_rst_resync: entity work.gc_sync_register inst_vme_rst_resync: entity work.gc_sync_register
generic map (g_width => 1) generic map (g_width => 1)
port map (clk_i => clk_i, port map (clk_i => clk_i,
...@@ -272,7 +272,7 @@ begin ...@@ -272,7 +272,7 @@ begin
port map (clk_i => clk_i, port map (clk_i => clk_i,
rst_n_a_i => rst_n_i, rst_n_a_i => rst_n_i,
d_i(0) => vme_i.iackin_n, d_i(0) => vme_i.iackin_n,
q_o(0) => s_VME_IACKIN_n); q_o(0) => s_vme_iackin_n);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- VME Bus -- VME Bus
...@@ -286,28 +286,28 @@ begin ...@@ -286,28 +286,28 @@ begin
rst_n_i => s_reset_n, rst_n_i => s_reset_n,
-- VME -- VME
VME_AS_n_i => s_VME_AS_n, vme_as_n_i => s_vme_as_n,
VME_LWORD_n_o => vme_o.lword_n, vme_lword_n_o => vme_o.lword_n,
VME_LWORD_n_i => vme_i.lword_n, vme_lword_n_i => vme_i.lword_n,
VME_RETRY_n_o => vme_o.retry_n, vme_retry_n_o => vme_o.retry_n,
VME_RETRY_OE_o => vme_o.retry_oe, vme_retry_oe_o => vme_o.retry_oe,
VME_WRITE_n_i => s_VME_WRITE_n, vme_write_n_i => s_vme_write_n,
VME_DS_n_i => s_VME_DS_n, vme_ds_n_i => s_vme_ds_n,
VME_DTACK_n_o => vme_o.dtack_n, vme_dtack_n_o => vme_o.dtack_n,
VME_DTACK_OE_o => vme_o.dtack_oe, vme_dtack_oe_o => vme_o.dtack_oe,
VME_BERR_n_o => s_vme_berr_n, vme_berr_n_o => s_vme_berr_n,
VME_ADDR_i => vme_i.addr, vme_addr_i => vme_i.addr,
VME_ADDR_o => vme_o.addr, vme_addr_o => vme_o.addr,
VME_ADDR_DIR_o => vme_o.addr_dir, vme_addr_dir_o => vme_o.addr_dir,
VME_ADDR_OE_N_o => vme_o.addr_oe_n, vme_addr_oe_n_o => vme_o.addr_oe_n,
VME_DATA_i => vme_i.data, vme_data_i => vme_i.data,
VME_DATA_o => vme_o.data, vme_data_o => vme_o.data,
VME_DATA_DIR_o => vme_o.data_dir, vme_data_dir_o => vme_o.data_dir,
VME_DATA_OE_N_o => vme_o.data_oe_n, vme_data_oe_n_o => vme_o.data_oe_n,
VME_AM_i => vme_i.am, vme_am_i => vme_i.am,
VME_IACKIN_n_i => s_VME_IACKIN_n, vme_iackin_n_i => s_vme_iackin_n,
VME_IACK_n_i => s_VME_IACK_n, vme_iack_n_i => s_vme_iack_n,
VME_IACKOUT_n_o => vme_o.iackout_n, vme_iackout_n_o => vme_o.iackout_n,
-- WB signals -- WB signals
wb_stb_o => wb_o.stb, wb_stb_o => wb_o.stb,
...@@ -337,19 +337,19 @@ begin ...@@ -337,19 +337,19 @@ begin
module_enable_i => s_module_enable, module_enable_i => s_module_enable,
bar_i => s_bar, bar_i => s_bar,
INT_Level_i => s_irq_level, int_level_i => s_irq_level,
INT_Vector_i => s_irq_vector, int_vector_i => s_irq_vector,
irq_pending_i => s_irq_pending, irq_pending_i => s_irq_pending,
irq_ack_o => s_irq_ack); irq_ack_o => s_irq_ack);
s_reset_n <= rst_n_i and s_VME_RST_n; s_reset_n <= rst_n_i and s_vme_rst_n;
rst_n_o <= s_reset_n and (not s_module_reset); rst_n_o <= s_reset_n and (not s_module_reset);
vme_o.berr_n <= s_vme_berr_n; vme_o.berr_n <= s_vme_berr_n;
inst_vme_funct_match : entity work.vme_funct_match inst_vme_funct_match : entity work.vme_funct_match
generic map ( generic map (
g_decoder => g_decoder, g_DECODER => g_DECODER,
g_DECODE_AM => g_DECODE_AM g_DECODE_AM => g_DECODE_AM
) )
port map ( port map (
...@@ -380,11 +380,11 @@ begin ...@@ -380,11 +380,11 @@ begin
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => s_reset_n, rst_n_i => s_reset_n,
INT_Level_i => s_irq_level, int_level_i => s_irq_level,
INT_Req_i => int_i, int_req_i => int_i,
irq_pending_o => s_irq_pending, irq_pending_o => s_irq_pending,
irq_ack_i => s_irq_ack, irq_ack_i => s_irq_ack,
VME_IRQ_n_o => vme_o.irq_n vme_irq_n_o => vme_o.irq_n
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -405,7 +405,7 @@ begin ...@@ -405,7 +405,7 @@ begin
g_END_USER_CSR => g_END_USER_CSR, g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN, g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN, g_END_SN => g_END_SN,
g_decoder => g_decoder g_DECODER => g_DECODER
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
......
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