Commit a3b2fde3 authored by Tom Levens's avatar Tom Levens

Normalise all constants and generics to uppercase

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent de63753d
This diff is collapsed.
...@@ -308,7 +308,7 @@ begin ...@@ -308,7 +308,7 @@ begin
-- Check if the CR/CSR space is addressed -- Check if the CR/CSR space is addressed
Confaccess <= '1' Confaccess <= '1'
when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_CR_CSR when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_AM_CR_CSR
else '0'; else '0';
end Behavioral; end Behavioral;
...@@ -136,7 +136,7 @@ begin ...@@ -136,7 +136,7 @@ begin
elsif decode = '1' then elsif decode = '1' then
for i in AmMatch'range loop for i in AmMatch'range loop
if DFS_i(i) = '1' then if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '0' then if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i); AmMatch(i) <= s_amcap_match(i);
else else
...@@ -150,7 +150,7 @@ begin ...@@ -150,7 +150,7 @@ begin
end if; end if;
end if; end if;
else else
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '1' then if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i); AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else else
AmMatch(i) <= s_amcap_match(i); AmMatch(i) <= s_amcap_match(i);
......
...@@ -38,8 +38,8 @@ use work.vme64x_pack.all; ...@@ -38,8 +38,8 @@ use work.vme64x_pack.all;
entity VME_CRAM is entity VME_CRAM is
generic ( generic (
g_beg_cram : std_logic_vector(23 downto 0); g_BEG_CRAM : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0) g_END_CRAM : std_logic_vector(23 downto 0)
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -52,7 +52,7 @@ end VME_CRAM; ...@@ -52,7 +52,7 @@ end VME_CRAM;
architecture rtl of VME_CRAM is architecture rtl of VME_CRAM is
type t_cram is array (f_size(g_beg_cram, g_end_cram)-1 downto 0) type t_cram is array (f_size(g_BEG_CRAM, g_END_CRAM)-1 downto 0)
of std_logic_vector(7 downto 0); of std_logic_vector(7 downto 0);
signal s_cram : t_cram; signal s_cram : t_cram;
......
This diff is collapsed.
...@@ -318,7 +318,7 @@ begin ...@@ -318,7 +318,7 @@ begin
s_FUNC_ADEM(7) <= unsigned(Adem7); s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(ADEM_DFS); DFS_o(i) <= s_FUNC_ADEM(i)(c_ADEM_DFS);
end generate GDFS; end generate GDFS;
GADER_64 : for i in 0 to 6 generate GADER_64 : for i in 0 to 6 generate
......
...@@ -129,7 +129,7 @@ use work.vme64x_pack.all; ...@@ -129,7 +129,7 @@ use work.vme64x_pack.all;
entity VME_IRQ_Controller is entity VME_IRQ_Controller is
generic ( generic (
g_retry_timeout : integer range 1024 to 16777215 g_RETRY_TIMEOUT : integer range 1024 to 16777215
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -224,7 +224,7 @@ begin ...@@ -224,7 +224,7 @@ begin
retry_state <= WAIT_IRQ; retry_state <= WAIT_IRQ;
else else
retry_count <= retry_count + 1; retry_count <= retry_count + 1;
if (retry_count = g_retry_timeout) then if (retry_count = g_RETRY_TIMEOUT) then
retry_state <= WAIT_IRQ; retry_state <= WAIT_IRQ;
end if; end if;
end if; end if;
......
...@@ -17,14 +17,14 @@ ...@@ -17,14 +17,14 @@
-- To achieve the previous memory map layout, it is necessary to set the -- To achieve the previous memory map layout, it is necessary to set the
-- following generics on the VME64xCore_Top: -- following generics on the VME64xCore_Top:
-- --
-- g_beg_user_csr => x"07ff33", -- g_BEG_USER_CSR => x"07ff33",
-- g_end_user_csr => x"07ff5f", -- g_END_USER_CSR => x"07ff5f",
-- --
-- However, for new designs it would be better to choose somewhere outside -- However, for new designs it would be better to choose somewhere outside
-- the reserved area (from x"7fc00" to x"7ff5f"). For example: -- the reserved area (from x"7fc00" to x"7ff5f"). For example:
-- --
-- g_beg_user_csr => x"07fbd3", -- g_BEG_USER_CSR => x"07fbd3",
-- g_end_user_csr => x"07fbff", -- g_END_USER_CSR => x"07fbff",
-- --
-- The following registers are implemented: -- The following registers are implemented:
-- _ -- _
...@@ -70,7 +70,7 @@ use work.vme64x_pack.all; ...@@ -70,7 +70,7 @@ use work.vme64x_pack.all;
entity VME_User_CSR is entity VME_User_CSR is
generic ( generic (
g_wb_data_width : integer g_WB_DATA_WIDTH : integer
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -102,7 +102,7 @@ begin ...@@ -102,7 +102,7 @@ begin
s_addr <= unsigned(addr_i); s_addr <= unsigned(addr_i);
s_reg_wb32bits <= x"01" when g_wb_data_width = 32 else x"00"; s_reg_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
-- Write -- Write
process (clk_i) process (clk_i)
...@@ -115,9 +115,9 @@ begin ...@@ -115,9 +115,9 @@ begin
else else
if we_i = '1' then if we_i = '1' then
case s_addr is case s_addr is
when c_addr_irq_vector(18 downto 2) => s_reg_irq_vector <= data_i; when c_ADDR_IRQ_VECTOR(18 downto 2) => s_reg_irq_vector <= data_i;
when c_addr_irq_level(18 downto 2) => s_reg_irq_level <= data_i; when c_ADDR_IRQ_LEVEL(18 downto 2) => s_reg_irq_level <= data_i;
when c_addr_endian(18 downto 2) => s_reg_endian <= data_i; when c_ADDR_ENDIAN(18 downto 2) => s_reg_endian <= data_i;
when others => null; when others => null;
end case; end case;
end if; end if;
...@@ -137,17 +137,17 @@ begin ...@@ -137,17 +137,17 @@ begin
data_o <= x"00"; data_o <= x"00";
else else
case s_addr is case s_addr is
when c_addr_irq_vector(18 downto 2) => data_o <= s_reg_irq_vector; when c_ADDR_IRQ_VECTOR(18 downto 2) => data_o <= s_reg_irq_vector;
when c_addr_irq_level(18 downto 2) => data_o <= s_reg_irq_level; when c_ADDR_IRQ_LEVEL(18 downto 2) => data_o <= s_reg_irq_level;
when c_addr_endian(18 downto 2) => data_o <= s_reg_endian; when c_ADDR_ENDIAN(18 downto 2) => data_o <= s_reg_endian;
when c_addr_time0_ns(18 downto 2) => data_o <= time_i( 7 downto 0); when c_ADDR_TIME0_NS(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_addr_time1_ns(18 downto 2) => data_o <= time_i(15 downto 8); when c_ADDR_TIME1_NS(18 downto 2) => data_o <= time_i(15 downto 8);
when c_addr_time2_ns(18 downto 2) => data_o <= time_i(23 downto 16); when c_ADDR_TIME2_NS(18 downto 2) => data_o <= time_i(23 downto 16);
when c_addr_time3_ns(18 downto 2) => data_o <= time_i(31 downto 24); when c_ADDR_TIME3_NS(18 downto 2) => data_o <= time_i(31 downto 24);
when c_addr_time4_ns(18 downto 2) => data_o <= time_i(39 downto 32); when c_ADDR_TIME4_NS(18 downto 2) => data_o <= time_i(39 downto 32);
when c_addr_bytes0(18 downto 2) => data_o <= bytes_i( 7 downto 0); when c_ADDR_BYTES0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_addr_bytes1(18 downto 2) => data_o <= bytes_i(15 downto 8); when c_ADDR_BYTES1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_addr_wb32bits(18 downto 2) => data_o <= s_reg_wb32bits; when c_ADDR_WB32BITS(18 downto 2) => data_o <= s_reg_wb32bits;
when others => data_o <= x"ff"; when others => data_o <= x"ff";
end case; end case;
end if; end if;
......
...@@ -73,8 +73,8 @@ use work.vme64x_pack.all; ...@@ -73,8 +73,8 @@ use work.vme64x_pack.all;
entity VME_Wb_master is entity VME_Wb_master is
generic ( generic (
g_wb_data_width : integer; g_WB_DATA_WIDTH : integer;
g_wb_addr_width : integer g_WB_ADDR_WIDTH : integer
); );
port ( port (
memReq_i : in std_logic; memReq_i : in std_logic;
...@@ -95,11 +95,11 @@ entity VME_Wb_master is ...@@ -95,11 +95,11 @@ entity VME_Wb_master is
err_i : in std_logic; err_i : in std_logic;
cyc_o : out std_logic; cyc_o : out std_logic;
memReq_o : out std_logic; memReq_o : out std_logic;
WBdata_o : out std_logic_vector(g_wb_data_width-1 downto 0); WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width-1 downto 0); wbData_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width-1 downto 0); locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
memAckWB_i : in std_logic; memAckWB_i : in std_logic;
WbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0); WbSel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
RW_o : out std_logic RW_o : out std_logic
); );
end VME_Wb_master; end VME_Wb_master;
...@@ -111,7 +111,7 @@ architecture Behavioral of VME_Wb_master is ...@@ -111,7 +111,7 @@ architecture Behavioral of VME_Wb_master is
signal s_AckWithError : std_logic; signal s_AckWithError : std_logic;
signal s_wbData_i : std_logic_vector(63 downto 0); signal s_wbData_i : std_logic_vector(63 downto 0);
signal s_select : std_logic_vector(8 downto 0); signal s_select : std_logic_vector(8 downto 0);
signal s_DATi_sample : std_logic_vector(g_wb_data_width-1 downto 0); signal s_DATi_sample : std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
begin begin
...@@ -153,11 +153,11 @@ begin ...@@ -153,11 +153,11 @@ begin
end process; end process;
-- shift data and address for WB data bus 64 bits -- shift data and address for WB data bus 64 bits
gen64: if (g_wb_data_width = 64) generate gen64: if (g_WB_DATA_WIDTH = 64) generate
process (clk_i) process (clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_wb_addr_width)); locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_WB_ADDR_WIDTH));
end if; end if;
end process; end process;
...@@ -226,11 +226,11 @@ begin ...@@ -226,11 +226,11 @@ begin
end generate gen64; end generate gen64;
-- shift data and address for WB data bus 32 bits -- shift data and address for WB data bus 32 bits
gen32: if (g_wb_data_width = 32) generate gen32: if (g_WB_DATA_WIDTH = 32) generate
process (clk_i) process (clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2, g_wb_addr_width)); locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2, g_WB_ADDR_WIDTH));
end if; end if;
end process; end process;
...@@ -250,21 +250,21 @@ begin ...@@ -250,21 +250,21 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
case sel_i is case sel_i is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_wb_data_width)); when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width)); when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_wb_data_width)); when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_wb_data_width)); when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width)); when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_wb_data_width)); when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width)); when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width)); when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width)); when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when others => null; when others => null;
end case; end case;
......
...@@ -69,39 +69,39 @@ use work.vme64x_pack.all; ...@@ -69,39 +69,39 @@ use work.vme64x_pack.all;
entity VME_bus is entity VME_bus is
generic ( generic (
g_clock : integer; g_CLOCK_PERIOD : integer;
g_wb_data_width : integer; g_WB_DATA_WIDTH : integer;
g_wb_addr_width : integer; g_WB_ADDR_WIDTH : integer;
g_beg_user_cr : std_logic_vector( 23 downto 0); g_BEG_USER_CR : std_logic_vector( 23 downto 0);
g_end_user_cr : std_logic_vector( 23 downto 0); g_END_USER_CR : std_logic_vector( 23 downto 0);
g_beg_cram : std_logic_vector( 23 downto 0); g_BEG_CRAM : std_logic_vector( 23 downto 0);
g_end_cram : std_logic_vector( 23 downto 0); g_END_CRAM : std_logic_vector( 23 downto 0);
g_beg_user_csr : std_logic_vector( 23 downto 0); g_BEG_USER_CSR : std_logic_vector( 23 downto 0);
g_end_user_csr : std_logic_vector( 23 downto 0); g_END_USER_CSR : std_logic_vector( 23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0); g_F0_ADEM : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0); g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0); g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0); g_F1_ADEM : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0); g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0); g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0); g_F2_ADEM : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0); g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0); g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0); g_F3_ADEM : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0); g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0); g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0); g_F4_ADEM : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0); g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0); g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0); g_F5_ADEM : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0); g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0); g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0); g_F6_ADEM : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0); g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0); g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0); g_F7_ADEM : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0); g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0) g_F7_XAMCAP : std_logic_vector(255 downto 0)
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -134,10 +134,10 @@ entity VME_bus is ...@@ -134,10 +134,10 @@ entity VME_bus is
-- WB signals -- WB signals
stb_o : out std_logic; stb_o : out std_logic;
ack_i : in std_logic; ack_i : in std_logic;
dat_o : out std_logic_vector(g_wb_data_width-1 downto 0); dat_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width-1 downto 0); dat_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
adr_o : out std_logic_vector(g_wb_addr_width-1 downto 0); adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
sel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0); sel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
we_o : out std_logic; we_o : out std_logic;
cyc_o : out std_logic; cyc_o : out std_logic;
err_i : in std_logic; err_i : in std_logic;
...@@ -283,7 +283,7 @@ begin ...@@ -283,7 +283,7 @@ begin
-- Calculate the number of LATCH DS states necessary to match the timing -- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987. -- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
s_num_latchDS <= f_latchDS(g_clock); s_num_latchDS <= f_latchDS(g_CLOCK_PERIOD);
-- Used to drive the VME_ADDR_DIR_o -- Used to drive the VME_ADDR_DIR_o
s_is_d64 <= '1' when s_sel = "11111111" else '0'; s_is_d64 <= '1' when s_sel = "11111111" else '0';
...@@ -361,25 +361,25 @@ begin ...@@ -361,25 +361,25 @@ begin
s_addressingTypeSelect <= s_AMlatched; s_addressingTypeSelect <= s_AMlatched;
with s_addressingTypeSelect select s_addressingType <= with s_addressingTypeSelect select s_addressingType <=
A24 when c_A24_S_sup, A24 when c_AM_A24_S_SUP,
A24 when c_A24_S, A24 when c_AM_A24_S,
A24_BLT when c_A24_BLT, A24_BLT when c_AM_A24_BLT,
A24_BLT when c_A24_BLT_sup, A24_BLT when c_AM_A24_BLT_SUP,
A24_MBLT when c_A24_MBLT, A24_MBLT when c_AM_A24_MBLT,
A24_MBLT when c_A24_MBLT_sup, A24_MBLT when c_AM_A24_MBLT_SUP,
CR_CSR when c_CR_CSR, CR_CSR when c_AM_CR_CSR,
A16 when c_A16, A16 when c_AM_A16,
A16 when c_A16_sup, A16 when c_AM_A16_SUP,
A32 when c_A32, A32 when c_AM_A32,
A32 when c_A32_sup, A32 when c_AM_A32_SUP,
A32_BLT when c_A32_BLT, A32_BLT when c_AM_A32_BLT,
A32_BLT when c_A32_BLT_sup, A32_BLT when c_AM_A32_BLT_SUP,
A32_MBLT when c_A32_MBLT, A32_MBLT when c_AM_A32_MBLT,
A32_MBLT when c_A32_MBLT_sup, A32_MBLT when c_AM_A32_MBLT_SUP,
A64 when c_A64, A64 when c_AM_A64,
A64_BLT when c_A64_BLT, A64_BLT when c_AM_A64_BLT,
A64_MBLT when c_A64_MBLT, A64_MBLT when c_AM_A64_MBLT,
TWOedge when c_TWOedge, TWOedge when c_AM_TWOEDGE,
AM_Error when others; AM_Error when others;
-- Transfer type decoder -- Transfer type decoder
...@@ -754,7 +754,7 @@ begin ...@@ -754,7 +754,7 @@ begin
(s_blockTransferLimit = '1') or (s_blockTransferLimit = '1') or
(s_transferType = BLT and (not(s_typeOfDataTransfer = D32 or s_typeOfDataTransfer = D64))) or (s_transferType = BLT and (not(s_typeOfDataTransfer = D32 or s_typeOfDataTransfer = D64))) or
(s_transferType = MBLT and s_typeOfDataTransfer /= D64) or (s_transferType = MBLT and s_typeOfDataTransfer /= D64) or
(s_is_d64 = '1' and g_wb_data_width = 32) (s_is_d64 = '1' and g_WB_DATA_WIDTH = 32)
then then
s_BERRcondition <= '1'; s_BERRcondition <= '1';
else else
...@@ -1072,8 +1072,8 @@ begin ...@@ -1072,8 +1072,8 @@ begin
Inst_Wb_master : VME_Wb_master Inst_Wb_master : VME_Wb_master
generic map ( generic map (
g_wb_data_width => g_wb_data_width, g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_wb_addr_width => g_wb_addr_width g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH
) )
port map ( port map (
memReq_i => s_memReq, memReq_i => s_memReq,
...@@ -1128,30 +1128,30 @@ begin ...@@ -1128,30 +1128,30 @@ begin
Ader5 => f5_ader_i, Ader5 => f5_ader_i,
Ader6 => f6_ader_i, Ader6 => f6_ader_i,
Ader7 => f7_ader_i, Ader7 => f7_ader_i,
Adem0 => g_f0_adem, Adem0 => g_F0_ADEM,
Adem1 => g_f1_adem, Adem1 => g_F1_ADEM,
Adem2 => g_f2_adem, Adem2 => g_F2_ADEM,
Adem3 => g_f3_adem, Adem3 => g_F3_ADEM,
Adem4 => g_f4_adem, Adem4 => g_F4_ADEM,
Adem5 => g_f5_adem, Adem5 => g_F5_ADEM,
Adem6 => g_f6_adem, Adem6 => g_F6_ADEM,
Adem7 => g_f7_adem, Adem7 => g_F7_ADEM,
AmCap0 => g_f0_amcap, AmCap0 => g_F0_AMCAP,
AmCap1 => g_f1_amcap, AmCap1 => g_F1_AMCAP,
AmCap2 => g_f2_amcap, AmCap2 => g_F2_AMCAP,
AmCap3 => g_f3_amcap, AmCap3 => g_F3_AMCAP,
AmCap4 => g_f4_amcap, AmCap4 => g_F4_AMCAP,
AmCap5 => g_f5_amcap, AmCap5 => g_F5_AMCAP,
AmCap6 => g_f6_amcap, AmCap6 => g_F6_AMCAP,
AmCap7 => g_f7_amcap, AmCap7 => g_F7_AMCAP,
XAmCap0 => g_f0_xamcap, XAmCap0 => g_F0_XAMCAP,
XAmCap1 => g_f1_xamcap, XAmCap1 => g_F1_XAMCAP,
XAmCap2 => g_f2_xamcap, XAmCap2 => g_F2_XAMCAP,
XAmCap3 => g_f3_xamcap, XAmCap3 => g_F3_XAMCAP,
XAmCap4 => g_f4_xamcap, XAmCap4 => g_F4_XAMCAP,
XAmCap5 => g_f5_xamcap, XAmCap5 => g_F5_XAMCAP,
XAmCap6 => g_f6_xamcap, XAmCap6 => g_F6_XAMCAP,
XAmCap7 => g_f7_xamcap, XAmCap7 => g_F7_XAMCAP,
Am => s_AMlatched, Am => s_AMlatched,
XAm => std_logic_vector(s_XAM), XAm => std_logic_vector(s_XAM),
BAR_i => bar_i, BAR_i => bar_i,
......
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...@@ -78,55 +78,55 @@ package xvme64x_core_pkg is ...@@ -78,55 +78,55 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component xvme64x_core component xvme64x_core
generic ( generic (
g_clock_period : integer := c_clk_period; g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_wb_data_width : integer := c_wishbone_data_width; g_WB_DATA_WIDTH : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width; g_WB_ADDR_WIDTH : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false; g_USER_CSR_EXT : boolean := false;
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id; g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id; g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id; g_REVISION_ID : std_logic_vector(31 downto 0) := c_REVISION_ID;
g_program_id : std_logic_vector(7 downto 0) := c_program_id; g_PROGRAM_ID : std_logic_vector(7 downto 0) := c_PROGRAM_ID;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000"; g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000"; g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000"; g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003"; g_BEG_CRAM : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff"; g_END_CRAM : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33"; g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f"; g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000"; g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000"; g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00"; g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000"; g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000"; g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84"; g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000"; g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"; g_F7_XAMCAP : std_logic_vector(255 downto 0)