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VME64x core
Commits
a90f3280
Commit
a90f3280
authored
Sep 14, 2017
by
Tristan Gingold
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Plain Diff
remove DFS, XAM, FAF, EFM. Address width is always 32.
parent
abcf3e01
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Showing
7 changed files
with
84 additions
and
388 deletions
+84
-388
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+4
-54
VME_CR_CSR_Space.vhd
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+3
-50
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+55
-198
VME_Wb_master.vhd
hdl/vme64x-core/rtl/VME_Wb_master.vhd
+5
-3
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+10
-12
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+7
-39
top_tb.vhd
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
+0
-32
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
a90f3280
...
...
@@ -155,49 +155,41 @@ entity VME64xCore_Top is
-- Function 0
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 1
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F1_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 2
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 3
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 4
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 5
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 6
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 7
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
port
(
...
...
@@ -269,24 +261,6 @@ entity VME64xCore_Top is
-- Functions
function_o
:
out
std_logic_vector
(
3
downto
0
);
f0_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f0_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
-- IRQ Generator
irq_ack_o
:
out
std_logic
;
-- when the IRQ controller acknowledges the
-- Interrupt cycle it sends a pulse to the
...
...
@@ -335,13 +309,12 @@ architecture RTL of VME64xCore_Top is
signal
s_user_csr_we
:
std_logic
;
-- Function decoders
signal
s_addr_decoder_i
:
std_logic_vector
(
63
downto
0
);
signal
s_addr_decoder_o
:
std_logic_vector
(
63
downto
0
);
signal
s_addr_decoder_i
:
std_logic_vector
(
31
downto
0
);
signal
s_addr_decoder_o
:
std_logic_vector
(
31
downto
0
);
signal
s_decode
:
std_logic
;
signal
s_sel
:
std_logic
;
signal
s_function
:
std_logic_vector
(
2
downto
0
);
signal
s_am
:
std_logic_vector
(
5
downto
0
);
signal
s_xam
:
std_logic_vector
(
7
downto
0
);
-- Oversampled input signals
signal
s_VME_RST_n
:
std_logic_vector
(
2
downto
0
);
...
...
@@ -362,25 +335,11 @@ architecture RTL of VME64xCore_Top is
g_F0_AMCAP
,
g_F1_AMCAP
,
g_F2_AMCAP
,
g_F3_AMCAP
,
g_F4_AMCAP
,
g_F5_AMCAP
,
g_F6_AMCAP
,
g_F7_AMCAP
);
constant
c_XAMCAP
:
t_xamcap_array
(
0
to
7
)
:
=
(
g_F0_XAMCAP
,
g_F1_XAMCAP
,
g_F2_XAMCAP
,
g_F3_XAMCAP
,
g_F4_XAMCAP
,
g_F5_XAMCAP
,
g_F6_XAMCAP
,
g_F7_XAMCAP
);
constant
c_DAWPR
:
t_dawpr_array
(
0
to
7
)
:
=
(
g_F0_DAWPR
,
g_F1_DAWPR
,
g_F2_DAWPR
,
g_F3_DAWPR
,
g_F4_DAWPR
,
g_F5_DAWPR
,
g_F6_DAWPR
,
g_F7_DAWPR
);
signal
s_faf_ader
:
t_ader_array
(
0
to
7
);
signal
s_dfs_adem
:
t_adem_array
(
0
to
7
);
begin
s_faf_ader
<=
(
f0_faf_ader_i
,
f1_faf_ader_i
,
f2_faf_ader_i
,
f3_faf_ader_i
,
f4_faf_ader_i
,
f5_faf_ader_i
,
f6_faf_ader_i
,
f7_faf_ader_i
);
s_dfs_adem
<=
(
f0_dfs_adem_i
,
f1_dfs_adem_i
,
f2_dfs_adem_i
,
f3_dfs_adem_i
,
f4_dfs_adem_i
,
f5_dfs_adem_i
,
f6_dfs_adem_i
,
f7_dfs_adem_i
);
------------------------------------------------------------------------------
-- Metastability
------------------------------------------------------------------------------
...
...
@@ -453,7 +412,6 @@ begin
addr_decoder_o
=>
s_addr_decoder_i
,
decode_o
=>
s_decode
,
am_o
=>
s_am
,
xam_o
=>
s_xam
,
sel_i
=>
s_sel
,
-- CR/CSR signals
...
...
@@ -476,8 +434,7 @@ begin
Inst_VME_Funct_Match
:
VME_Funct_Match
generic
map
(
g_ADEM
=>
c_ADEM
,
g_AMCAP
=>
c_AMCAP
,
g_XAMCAP
=>
c_XAMCAP
g_AMCAP
=>
c_AMCAP
)
port
map
(
clk_i
=>
clk_i
,
...
...
@@ -487,11 +444,7 @@ begin
addr_o
=>
s_addr_decoder_o
,
decode_i
=>
s_decode
,
am_i
=>
s_am
,
xam_i
=>
s_xam
,
ader_i
=>
s_ader
,
dfs_adem_i
=>
s_dfs_adem
,
sel_o
=>
s_sel
,
function_o
=>
s_function
);
...
...
@@ -568,7 +521,6 @@ begin
g_END_SN
=>
g_END_SN
,
g_ADEM
=>
c_ADEM
,
g_AMCAP
=>
c_AMCAP
,
g_XAMCAP
=>
c_XAMCAP
,
g_DAWPR
=>
c_DAWPR
)
port
map
(
...
...
@@ -596,9 +548,7 @@ begin
user_cr_addr_o
=>
user_cr_addr_o
,
user_cr_data_i
=>
user_cr_data_i
,
ader_o
=>
s_ader
,
faf_ader_i
=>
s_faf_ader
,
dfs_adem_i
=>
s_dfs_adem
ader_o
=>
s_ader
);
-- User CSR space
...
...
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @
a90f3280
...
...
@@ -124,7 +124,6 @@ entity VME_CR_CSR_Space is
g_END_SN
:
std_logic_vector
(
23
downto
0
);
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_XAMCAP
:
t_xamcap_array
(
0
to
7
);
g_DAWPR
:
t_dawpr_array
(
0
to
7
)
);
port
(
...
...
@@ -152,9 +151,7 @@ entity VME_CR_CSR_Space is
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
);
ader_o
:
out
t_ader_array
(
0
to
7
);
faf_ader_i
:
in
t_ader_array
(
0
to
7
);
dfs_adem_i
:
in
t_adem_array
(
0
to
7
)
ader_o
:
out
t_ader_array
(
0
to
7
)
);
end
VME_CR_CSR_Space
;
...
...
@@ -167,7 +164,6 @@ architecture rtl of VME_CR_CSR_Space is
signal
s_reg_cram_owner
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_usr_bit_reg
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_ader
:
t_ader_array
(
0
to
7
);
signal
s_ader
:
t_ader_array
(
0
to
7
);
-- CR/CSR
signal
s_cr_access
:
std_logic
;
...
...
@@ -282,7 +278,6 @@ architecture rtl of VME_CR_CSR_Space is
for
i
in
0
to
7
loop
cr
(
16
#
040
#+
i
)
:
=
g_DAWPR
(
i
);
-- Function X DAWPR
cr
(
16
#
048
#+
i
*
8
to
16
#
04
f
#+
i
*
8
)
:
=
f_cr_vec
(
g_AMCAP
(
i
));
-- Function X AMCAP
cr
(
16
#
088
#+
i
*
32
to
16
#
0
a7
#+
i
*
32
)
:
=
f_cr_vec
(
g_XAMCAP
(
i
));
-- Function X XAMCAP
cr
(
16
#
188
#+
i
*
4
to
16
#
18
b
#+
i
*
4
)
:
=
f_cr_vec
(
g_ADEM
(
i
));
-- Function X ADEM
end
loop
;
for
i
in
1
to
cr
'length
-1
loop
...
...
@@ -396,49 +391,7 @@ begin
module_enable_o
<=
s_reg_bit_reg
(
c_ENABLE_BIT
);
vme_sysfail_ena_o
<=
s_reg_bit_reg
(
c_SYSFAIL_EN_BIT
);
module_reset_o
<=
s_reg_bit_reg
(
c_RESET_BIT
);
-- Handle DFS and FAF
process
(
s_reg_ader
,
faf_ader_i
,
dfs_adem_i
)
variable
v_ader_b0
:
std_logic_vector
(
7
downto
0
);
begin
for
i
in
0
to
7
loop
-- When FAF function or upper bits of previous FAF function, readback
-- and output ADER given at the FAF inputs.
if
(
i
/=
0
and
g_ADEM
(
i
-1
)(
c_ADEM_EFM
)
=
'1'
and
g_ADEM
(
i
-1
)(
c_ADEM_FAF
)
=
'1'
)
or
((
i
=
0
or
g_ADEM
(
i
-1
)(
c_ADEM_EFM
)
=
'0'
)
and
g_ADEM
(
i
)(
c_ADEM_FAF
)
=
'1'
)
then
s_ader
(
i
)
<=
faf_ader_i
(
i
);
ader_o
(
i
)
<=
faf_ader_i
(
i
);
-- When upper bits of previous DFS function and DFSR enabled, readback
-- the ADEM value and output zero.
elsif
i
/=
0
and
g_ADEM
(
i
-1
)(
c_ADEM_EFM
)
=
'1'
and
g_ADEM
(
i
-1
)(
c_ADEM_DFS
)
=
'1'
and
s_reg_ader
(
i
-1
)(
c_ADER_DFSR
)
=
'1'
then
s_ader
(
i
)
<=
dfs_adem_i
(
i
);
ader_o
(
i
)
<=
(
others
=>
'0'
);
-- When a DFS function and DFSR enabled, readback the ADEM and output
-- zero.
elsif
(
i
=
0
or
g_ADEM
(
i
-1
)(
c_ADEM_EFM
)
=
'0'
)
and
g_ADEM
(
i
)(
c_ADEM_DFS
)
=
'1'
and
s_reg_ader
(
i
)(
c_ADER_DFSR
)
=
'1'
then
v_ader_b0
:
=
(
c_ADER_DFSR
=>
s_reg_ader
(
i
)(
c_ADER_DFSR
),
others
=>
'0'
);
s_ader
(
i
)
<=
dfs_adem_i
(
i
)(
c_ADEM_M
)
&
v_ader_b0
;
ader_o
(
i
)
<=
(
others
=>
'0'
);
-- In all other cases, readback and output the ADER register value.
else
s_ader
(
i
)
<=
s_reg_ader
(
i
);
ader_o
(
i
)
<=
s_reg_ader
(
i
);
end
if
;
end
loop
;
end
process
;
ader_o
<=
s_reg_ader
;
-- Read
process
(
clk_i
)
...
...
@@ -473,7 +426,7 @@ begin
v_addr
:
=
s_addr
(
18
downto
2
)
-
to_unsigned
(
c_ADER_REG_BEG
,
17
);
v_index
:
=
to_integer
(
v_addr
(
6
downto
4
));
v_byte
:
=
3
-
to_integer
(
v_addr
(
3
downto
2
));
s_csr_data
<=
s_ader
(
v_index
)(
8
*
v_byte
+
7
downto
8
*
v_byte
);
s_csr_data
<=
s_
reg_
ader
(
v_index
)(
8
*
v_byte
+
7
downto
8
*
v_byte
);
when
others
=>
s_csr_data
<=
c_UNUSED
;
...
...
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
a90f3280
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @
a90f3280
...
...
@@ -85,7 +85,7 @@ entity VME_Wb_master is
sel_i
:
in
std_logic_vector
(
7
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
63
downto
0
);
locDataOut_o
:
out
std_logic_vector
(
63
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
63
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
31
downto
0
);
memAckWb_o
:
out
std_logic
;
err_o
:
out
std_logic
;
rty_o
:
out
std_logic
;
...
...
@@ -157,7 +157,8 @@ begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
locAddr_o
<=
std_logic_vector
(
resize
(
unsigned
(
rel_locAddr_i
)
srl
3
,
g_WB_ADDR_WIDTH
));
locAddr_o
(
63
downto
29
)
<=
(
others
=>
'0'
);
locAddr_o
(
28
downto
0
)
<=
rel_locAddr_i
(
31
downto
3
);
end
if
;
end
process
;
...
...
@@ -230,7 +231,8 @@ begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
locAddr_o
<=
std_logic_vector
(
resize
(
unsigned
(
rel_locAddr_i
)
srl
2
,
g_WB_ADDR_WIDTH
));
locAddr_o
(
31
downto
30
)
<=
(
others
=>
'0'
);
locAddr_o
(
29
downto
0
)
<=
rel_locAddr_i
(
31
downto
2
);
end
if
;
end
process
;
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
a90f3280
...
...
@@ -114,8 +114,8 @@ entity VME_bus is
stall_i
:
in
std_logic
;
-- Function decoder
addr_decoder_i
:
in
std_logic_vector
(
63
downto
0
);
addr_decoder_o
:
out
std_logic_vector
(
63
downto
0
);
addr_decoder_i
:
in
std_logic_vector
(
31
downto
0
);
addr_decoder_o
:
out
std_logic_vector
(
31
downto
0
);
decode_o
:
out
std_logic
;
am_o
:
out
std_logic_vector
(
5
downto
0
);
xam_o
:
out
std_logic_vector
(
7
downto
0
);
...
...
@@ -144,14 +144,14 @@ architecture RTL of VME_bus is
-- Local data & address
signal
s_locDataIn
:
std_logic_vector
(
63
downto
0
);
signal
s_locDataOut
:
std_logic_vector
(
63
downto
0
);
-- Local data
signal
s_locAddr
:
std_logic_vector
(
63
downto
0
);
-- Local address
signal
s_locAddr
:
std_logic_vector
(
31
downto
0
);
-- Local address
signal
s_DataShift
:
std_logic
;
signal
s_locDataOutSwap
:
std_logic_vector
(
63
downto
0
);
signal
s_locDataInSwap
:
std_logic_vector
(
63
downto
0
);
signal
s_locDataOutWb
:
std_logic_vector
(
63
downto
0
);
-- VME latched signals
signal
s_ADDRlatched
:
std_logic_vector
(
63
downto
1
);
signal
s_ADDRlatched
:
std_logic_vector
(
31
downto
1
);
signal
s_LWORDlatched
:
std_logic
;
signal
s_DSlatched
:
std_logic_vector
(
1
downto
0
);
signal
s_AMlatched
:
std_logic_vector
(
5
downto
0
);
...
...
@@ -408,7 +408,7 @@ begin
s_mainFSMstate
<=
REFORMAT_ADDRESS
;
-- Store ADDR, AM and LWORD
s_ADDRlatched
<=
VME_DATA_i
&
VME_ADDR_i
;
s_ADDRlatched
<=
VME_ADDR_i
;
s_LWORDlatched
<=
VME_LWORD_n_i
;
s_AMlatched
<=
VME_AM_i
;
...
...
@@ -420,13 +420,11 @@ begin
-- Reformat address according to the mode (A16, A24, A32 or A64)
case
s_addrWidth
is
when
"00"
=>
s_ADDRlatched
(
63
downto
16
)
<=
(
others
=>
'0'
);
-- A16
s_ADDRlatched
(
31
downto
16
)
<=
(
others
=>
'0'
);
-- A16
when
"01"
=>
s_ADDRlatched
(
63
downto
24
)
<=
(
others
=>
'0'
);
-- A24
when
"10"
=>
s_ADDRlatched
(
63
downto
32
)
<=
(
others
=>
'0'
);
-- A32
when
others
=>
null
;
-- A64
s_ADDRlatched
(
31
downto
24
)
<=
(
others
=>
'0'
);
-- A24
when
others
=>
-- A32
null
;
end
case
;
s_mainFSMstate
<=
DECODE_ACCESS_0
;
...
...
@@ -451,7 +449,7 @@ begin
-- card_sel = '1' it means WB application addressed
s_mainFSMstate
<=
WAIT_FOR_DS
;
-- Keep only the local part of the address
s_ADDRlatched
<=
addr_decoder_i
(
63
downto
1
);
s_ADDRlatched
<=
addr_decoder_i
(
31
downto
1
);
else
-- another board will answer; wait here the rising edge on
-- VME_AS_i (done by top if).
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
a90f3280
...
...
@@ -110,7 +110,6 @@ package vme64x_pack is
type
t_adem_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
31
downto
0
);
type
t_ader_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
31
downto
0
);
type
t_amcap_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
63
downto
0
);
type
t_xamcap_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
255
downto
0
);
type
t_dawpr_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
7
downto
0
);
------------------------------------------------------------------------------
...
...
@@ -138,35 +137,27 @@ package vme64x_pack is
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F1_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
port
(
...
...
@@ -219,22 +210,6 @@ package vme64x_pack is
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
f0_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f0_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
irq_ack_o
:
out
std_logic
;
irq_i
:
in
std_logic
);
...
...
@@ -280,11 +255,10 @@ package vme64x_pack is
err_i
:
in
std_logic
;
rty_i
:
in
std_logic
;
stall_i
:
in
std_logic
;
addr_decoder_i
:
in
std_logic_vector
(
63
downto
0
);
addr_decoder_o
:
out
std_logic_vector
(
63
downto
0
);
addr_decoder_i
:
in
std_logic_vector
(
31
downto
0
);
addr_decoder_o
:
out
std_logic_vector
(
31
downto
0
);
decode_o
:
out
std_logic
;
am_o
:
out
std_logic_vector
(
5
downto
0
);
xam_o
:
out
std_logic_vector
(
7
downto
0
);
sel_i
:
in
std_logic
;
cr_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
cr_csr_data_i
:
in
std_logic_vector
(
7
downto
0
);
...
...
@@ -299,19 +273,16 @@ package vme64x_pack is
component
VME_Funct_Match
is
generic
(
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_XAMCAP
:
t_xamcap_array
(
0
to
7
)
g_AMCAP
:
t_amcap_array
(
0
to
7
)
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
addr_i
:
in
std_logic_vector
(
63
downto
0
);
addr_o
:
out
std_logic_vector
(
63
downto
0
);
addr_i
:
in
std_logic_vector
(
31
downto
0
);
addr_o
:
out
std_logic_vector
(
31
downto
0
);
decode_i
:
in
std_logic
;
am_i
:
in
std_logic_vector
(
5
downto
0
);
xam_i
:
in
std_logic_vector
(
7
downto
0
);
ader_i
:
in
t_ader_array
(
0
to
7
);
dfs_adem_i
:
in
t_adem_array
(
0
to
7
);
sel_o
:
out
std_logic
;
function_o
:
out
std_logic_vector
(
2
downto
0
)
);
...
...
@@ -334,7 +305,6 @@ package vme64x_pack is
g_END_SN
:
std_logic_vector
(
23
downto
0
);
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_XAMCAP
:
t_xamcap_array
(
0
to
7
);
g_DAWPR
:
t_dawpr_array
(
0
to
7
)
);
port
(
...
...
@@ -357,9 +327,7 @@ package vme64x_pack is
user_csr_we_o
:
out
std_logic
;
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
);
ader_o
:
out
t_ader_array
(
0
to
7
);
faf_ader_i
:
in
t_ader_array
(
0
to
7
);
dfs_adem_i
:
in
t_adem_array
(
0
to
7
)
ader_o
:
out
t_ader_array
(
0
to
7
)
);
end
component
VME_CR_CSR_Space
;
...
...
@@ -395,7 +363,7 @@ package vme64x_pack is
BERRcondition_i
:
in
std_logic
;
sel_i
:
in
std_logic_vector
(
7
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
63
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
63
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
31
downto
0
);
RW_i
:
in
std_logic
;
stall_i
:
in
std_logic
;
rty_i
:
in
std_logic
;
...
...
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @
a90f3280
...
...
@@ -219,22 +219,6 @@ architecture behaviour of top_tb is
signal
user_cr_addr_o
:
std_logic_vector
(
18
downto
2
);
signal
user_cr_data_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
function_o
:
std_logic_vector
(
3
downto
0
);
signal
f0_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f1_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f2_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f3_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f4_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f5_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f6_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f7_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f0_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f1_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f2_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f3_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f4_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f5_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f6_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f7_dfs_adem_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
irq_ack_o
:
std_logic
;
signal
irq_i
:
std_logic
;
...
...
@@ -303,22 +287,6 @@ begin
user_cr_addr_o
=>
user_cr_addr_o
,
user_cr_data_i
=>
user_cr_data_i
,
function_o
=>
function_o
,
f0_faf_ader_i
=>
f0_faf_ader_i
,
f1_faf_ader_i
=>
f1_faf_ader_i
,
f2_faf_ader_i
=>
f2_faf_ader_i
,
f3_faf_ader_i
=>
f3_faf_ader_i
,
f4_faf_ader_i
=>
f4_faf_ader_i
,
f5_faf_ader_i
=>
f5_faf_ader_i
,
f6_faf_ader_i
=>
f6_faf_ader_i
,
f7_faf_ader_i
=>
f7_faf_ader_i
,
f0_dfs_adem_i
=>
f0_dfs_adem_i
,
f1_dfs_adem_i
=>
f1_dfs_adem_i
,
f2_dfs_adem_i
=>
f2_dfs_adem_i
,
f3_dfs_adem_i
=>
f3_dfs_adem_i
,
f4_dfs_adem_i
=>
f4_dfs_adem_i
,
f5_dfs_adem_i
=>
f5_dfs_adem_i
,
f6_dfs_adem_i
=>
f6_dfs_adem_i
,
f7_dfs_adem_i
=>
f7_dfs_adem_i
,
irq_ack_o
=>
irq_ack_o
,
irq_i
=>
irq_i
);
...
...
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