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VME64x core
Commits
ae18039d
Commit
ae18039d
authored
Jan 02, 2017
by
Tom Levens
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Removed unused debug signals from VME_bus.vhd
Signed-off-by:
Tom Levens
<
tom.levens@cern.ch
>
parent
dafbb793
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4 changed files
with
7 additions
and
32 deletions
+7
-32
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+4
-12
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+1
-14
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+1
-4
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+1
-2
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
ae18039d
...
...
@@ -183,11 +183,9 @@ entity VME64xCore_Top is
-- IRQ Generator
INT_ack_o
:
out
std_logic
;
-- when the IRQ controller acknowledges the Interrupt
-- cycle it sends a pulse to the IRQ Generator
IRQ_i
:
in
std_logic
;
-- Interrupt request; the IRQ Generator/your Wb application
IRQ_i
:
in
std_logic
-- Interrupt request; the IRQ Generator/your Wb application
-- sends a pulse to the IRQ Controller which asserts one of
-- the IRQ lines.
-- Added by Davide for debug:
debug
:
out
std_logic_vector
(
7
downto
0
)
);
end
VME64xCore_Top
;
...
...
@@ -255,8 +253,6 @@ architecture RTL of VME64xCore_Top is
signal
s_ModuleEnable
:
std_logic
;
signal
s_Endian
:
std_logic_vector
(
2
downto
0
);
signal
s_BAR
:
std_logic_vector
(
4
downto
0
);
signal
s_time
:
std_logic_vector
(
39
downto
0
);
signal
s_bytes
:
std_logic_vector
(
12
downto
0
);
-- Oversampled input signals
signal
VME_RST_n_oversampled
:
std_logic
;
...
...
@@ -410,11 +406,7 @@ begin
ModuleEnable
=>
s_ModuleEnable
,
Endian_i
=>
s_Endian
,
Sw_Reset
=>
s_Sw_Reset
,
BAR_i
=>
s_BAR
,
numBytes
=>
s_bytes
,
transfTime
=>
s_time
,
-- debug
leds
=>
debug
BAR_i
=>
s_BAR
);
---------------------------------------------------------------------------------
...
...
@@ -498,8 +490,8 @@ begin
Endian_o
=>
s_Endian
,
BAR_o
=>
s_BAR
,
INT_Level
=>
s_INT_Level
,
numBytes
=>
s_bytes
,
transfTime
=>
s_time
,
numBytes
=>
(
others
=>
'0'
)
,
transfTime
=>
(
others
=>
'0'
)
,
INT_Vector
=>
s_INT_Vector
);
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
ae18039d
...
...
@@ -34,15 +34,6 @@
-- one Slave can answer to the Master! |
-- In the right side you can see the WB Master who implements the Wb Pipelined |
-- single read/write protocol.
--
-- led 0 <-- error flag
-- led 1 <-- last access: CR/CSR
-- led 2 <-- last access: WB SINGLE access
-- led 3 <-- last access: WB BLT access
-- led 4 <-- last access: WB MBLT access
-- led 5 <-- WB data bus 32 bits
-- led 6 <-- Module enable
-- led 7 <-- flashing
-- Each VME board plugged in a slot acts as a VME slave module and it has only
-- one CR/CSR space (conforming with the specification) so only one FPGA at time
-- must drive the output lines on the VME bus; only one FPGA at time can carry
...
...
@@ -153,11 +144,7 @@ entity VME_bus is
ModuleEnable
:
in
std_logic
;
Endian_i
:
in
std_logic_vector
(
2
downto
0
);
Sw_Reset
:
in
std_logic
;
BAR_i
:
in
std_logic_vector
(
4
downto
0
);
numBytes
:
out
std_logic_vector
(
12
downto
0
)
:
=
(
others
=>
'0'
);
-- TODO: what's this?
transfTime
:
out
std_logic_vector
(
39
downto
0
)
:
=
(
others
=>
'0'
);
-- TODO: what's this?
-- Debug
leds
:
out
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
)
-- not used
BAR_i
:
in
std_logic_vector
(
4
downto
0
)
);
end
VME_bus
;
--===========================================================================
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
ae18039d
...
...
@@ -482,10 +482,7 @@ package vme64x_pack is
en_wr_CSR
:
out
std_logic
;
CrCsrOffsetAddr
:
out
std_logic_vector
(
18
downto
0
);
CSRData_o
:
out
std_logic_vector
(
7
downto
0
);
err_flag_o
:
out
std_logic
;
numBytes
:
out
std_logic_vector
(
12
downto
0
);
transfTime
:
out
std_logic_vector
(
39
downto
0
);
leds
:
out
std_logic_vector
(
7
downto
0
)
err_flag_o
:
out
std_logic
);
end
component
VME_bus
;
...
...
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
ae18039d
...
...
@@ -138,8 +138,7 @@ architecture wrapper of xvme64x_core is
WE_o
:
out
std_logic
;
STALL_i
:
in
std_logic
;
INT_ack_o
:
out
std_logic
;
IRQ_i
:
in
std_logic
;
debug
:
out
std_logic_vector
(
7
downto
0
));
IRQ_i
:
in
std_logic
);
end
component
;
signal
dat_out
,
dat_in
:
std_logic_vector
(
31
downto
0
);
...
...
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