Commit af4ec2d0 authored by Tom Levens's avatar Tom Levens

Major cleanup of VHDL code

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent ae18039d
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
--______________________________________________________________________________|
-- VME TO WB INTERFACE |
-- |
-- CERN,BE/CO-HT |
--______________________________________________________________________________|
-- File: VME_CRAM.vhd |
--______________________________________________________________________________|
-- Description: RAM memory
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CRAM (VME_CRAM.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: RAM memory
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_CRAM is
generic (dl : integer;
al : integer := f_log2_size(c_CRAM_SIZE)
);
port (clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al - 1 downto 0);
di : in std_logic_vector(dl - 1 downto 0);
dw : out std_logic_vector(dl - 1 downto 0)
);
end VME_CRAM;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture syn of VME_CRAM is
type ram_type is array (2**al - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal CRAM : ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
entity VME_CRAM is
generic (
dl : integer;
al : integer := f_log2_size(c_CRAM_SIZE)
);
port (
clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al-1 downto 0);
di : in std_logic_vector(dl-1 downto 0);
dw : out std_logic_vector(dl-1 downto 0)
);
end VME_CRAM;
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
CRAM(conv_integer(aw)) <= di;
end if;
dw <= CRAM(conv_integer(aw));
end if;
end process;
end syn;
--===========================================================================
-- Architecture end
--===========================================================================
architecture syn of VME_CRAM is
type ram_type is array (2**al-1 downto 0) of std_logic_vector (dl-1 downto 0);
signal CRAM : ram_type;
begin
process (clk) begin
if rising_edge(clk) then
if (we = '1') then
CRAM(to_integer(unsigned(aw))) <= di;
end if;
dw <= CRAM(to_integer(unsigned(aw)));
end if;
end process;
end syn;
This diff is collapsed.
This diff is collapsed.
--________________________________________________________________________________________________
-- VME TO WB INTERFACE
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
-- File: VME_CSR_pack.vhd
--________________________________________________________________________________________________
-- Description: This file defines the default configuration of the CSR space after power-up or
-- software reset.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your option)
-- any later version. This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
-- more details. You should have received a copy of the GNU Lesser General Public
-- License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- unit name: VME_CSR_pack (VME_CSR_pack.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: This file defines the default configuration of the CSR space
-- after power-up or software reset.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray :=
(
BAR => x"00", --CR/CSR BAR
BIT_SET_CLR_REG => x"00", --Bit set register -- 0x10=module enable
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"00", --A32_S "24"
FUNC0_ADER_1 =>x"00", -- "00"
FUNC0_ADER_2 =>x"00", -- "00"
FUNC0_ADER_3 =>x"00", -- "c0"
FUNC1_ADER_0 =>x"00", --A24_S "e4"
FUNC1_ADER_1 =>x"00", -- "00"
FUNC1_ADER_2 =>x"00", -- "c0"
FUNC1_ADER_3 =>x"00", -- "00"
FUNC2_ADER_0 =>x"00", --A16_S "a4"
FUNC2_ADER_1 =>x"00", -- "c0"
FUNC2_ADER_2 =>x"00", -- "00"
FUNC2_ADER_3 =>x"00", -- "00"
FUNC3_ADER_0 =>x"00", --A64_S "04"
FUNC3_ADER_1 =>x"00",
FUNC3_ADER_2 =>x"00",
FUNC3_ADER_3 =>x"00",
FUNC4_ADER_0 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_1 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_2 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_3 =>x"00", --used for decoding the FUNC3 "c0"
FUNC5_ADER_0 =>x"00",
FUNC5_ADER_1 =>x"00",
FUNC5_ADER_2 =>x"00",
FUNC5_ADER_3 =>x"00",
FUNC6_ADER_0 =>x"00",
FUNC6_ADER_1 =>x"00",
FUNC6_ADER_2 =>x"00",
FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level =>x"02",
WB32bits =>x"01", -- 32 bit WB of default
others => (others => '0'));
end VME_CSR_pack;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray := (
BAR => x"00", -- CR/CSR BAR
BIT_SET_CLR_REG => x"00", -- Bit set register
-- 0x10 = module enable
USR_BIT_SET_CLR_REG => x"00", -- Bit clear register
CRAM_OWNER => x"00", -- CRAM_OWNER
FUNC0_ADER_0 => x"00", -- A32_S "24"
FUNC0_ADER_1 => x"00", -- "00"
FUNC0_ADER_2 => x"00", -- "00"
FUNC0_ADER_3 => x"00", -- "c0"
FUNC1_ADER_0 => x"00", -- A24_S "e4"
FUNC1_ADER_1 => x"00", -- "00"
FUNC1_ADER_2 => x"00", -- "c0"
FUNC1_ADER_3 => x"00", -- "00"
FUNC2_ADER_0 => x"00", -- A16_S "a4"
FUNC2_ADER_1 => x"00", -- "c0"
FUNC2_ADER_2 => x"00", -- "00"
FUNC2_ADER_3 => x"00", -- "00"
FUNC3_ADER_0 => x"00", -- A64_S "04"
FUNC3_ADER_1 => x"00",
FUNC3_ADER_2 => x"00",
FUNC3_ADER_3 => x"00",
FUNC4_ADER_0 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_1 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_2 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_3 => x"00", -- used for decoding the FUNC3 "c0"
FUNC5_ADER_0 => x"00",
FUNC5_ADER_1 => x"00",
FUNC5_ADER_2 => x"00",
FUNC5_ADER_3 => x"00",
FUNC6_ADER_0 => x"00",
FUNC6_ADER_1 => x"00",
FUNC6_ADER_2 => x"00",
FUNC6_ADER_3 => x"00",
IRQ_Vector => x"00", -- "00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level => x"02",
WB32bits => x"01", -- 32 bit WB of default
others => (others => '0')
);
end VME_CSR_pack;
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment