Commit b5d758c9 authored by Tristan Gingold's avatar Tristan Gingold

Reduce a little bit more the number of warnings.

parent 8aaa3368
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
** VME64xCore_top.vhd ** VME64xCore_top.vhd
- Add generic/constant for number of supported functions and use it to limit size of ader/adem - Add generic/constant for number of supported functions and use it to limit size of ader/adem
arrays etc, in order to reduce number of warnings in ISE (from ~450 to ~50) arrays etc, in order to reduce number of warnings in ISE (from ~450 to ~50)
Ok. Done.
- gc_sync_register: does it even make sense? Slide #95 of NASA radiation tolerant design presentation: - gc_sync_register: does it even make sense? Slide #95 of NASA radiation tolerant design presentation:
https://indico.cern.ch/event/663761/contributions/2710422/attachments/1537821/2410163/Berg_SynchronousDesign_2017.pdf https://indico.cern.ch/event/663761/contributions/2710422/attachments/1537821/2410163/Berg_SynchronousDesign_2017.pdf
No problem, discussion about width postponed. No problem, discussion about width postponed.
......
...@@ -112,8 +112,8 @@ entity vme_bus is ...@@ -112,8 +112,8 @@ entity vme_bus is
wb_stall_i : in std_logic; wb_stall_i : in std_logic;
-- Function decoder -- Function decoder
addr_decoder_i : in std_logic_vector(31 downto 0); addr_decoder_i : in std_logic_vector(31 downto 1);
addr_decoder_o : out std_logic_vector(31 downto 0); addr_decoder_o : out std_logic_vector(31 downto 1);
decode_start_o : out std_logic; decode_start_o : out std_logic;
decode_done_i : in std_logic; decode_done_i : in std_logic;
am_o : out std_logic_vector( 5 downto 0); am_o : out std_logic_vector( 5 downto 0);
...@@ -427,7 +427,7 @@ begin ...@@ -427,7 +427,7 @@ begin
-- card_sel = '1' it means WB application addressed -- card_sel = '1' it means WB application addressed
s_card_sel <= '1'; s_card_sel <= '1';
-- Keep only the local part of the address. -- Keep only the local part of the address.
s_vme_addr_reg <= addr_decoder_i (31 downto 1); s_vme_addr_reg <= addr_decoder_i;
if VME_DS_n_i = "11" then if VME_DS_n_i = "11" then
s_mainFSMstate <= WAIT_FOR_DS; s_mainFSMstate <= WAIT_FOR_DS;
...@@ -755,7 +755,7 @@ begin ...@@ -755,7 +755,7 @@ begin
wb_dat_o <= s_locDataIn(31 downto 0); wb_dat_o <= s_locDataIn(31 downto 0);
-- Function Decoder -- Function Decoder
addr_decoder_o <= s_vme_addr_reg & '0'; addr_decoder_o <= s_vme_addr_reg;
am_o <= s_AMlatched; am_o <= s_AMlatched;
-- CR/CSR In/Out -- CR/CSR In/Out
......
...@@ -47,9 +47,9 @@ entity vme_funct_match is ...@@ -47,9 +47,9 @@ entity vme_funct_match is
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- Input address (to be decoded). -- Input address (to be decoded).
addr_i : in std_logic_vector(31 downto 0); addr_i : in std_logic_vector(31 downto 1);
-- Sub-address of the function (the part not masked by adem). -- Sub-address of the function (the part not masked by adem).
addr_o : out std_logic_vector(31 downto 0); addr_o : out std_logic_vector(31 downto 1);
decode_start_i : in std_logic; decode_start_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0); am_i : in std_logic_vector( 5 downto 0);
...@@ -115,7 +115,7 @@ begin ...@@ -115,7 +115,7 @@ begin
-- Address output latch -- Address output latch
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
process (clk_i) is process (clk_i) is
variable mask : std_logic_vector(31 downto 0); variable mask : std_logic_vector(31 downto 1);
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' or s_decode_start_1 = '0' then if rst_n_i = '0' or s_decode_start_1 = '0' then
......
...@@ -237,8 +237,8 @@ architecture rtl of xvme64x_core is ...@@ -237,8 +237,8 @@ architecture rtl of xvme64x_core is
signal s_user_csr_we : std_logic; signal s_user_csr_we : std_logic;
-- Function decoders -- Function decoders
signal s_addr_decoder_i : std_logic_vector(31 downto 0); signal s_addr_decoder_i : std_logic_vector(31 downto 1);
signal s_addr_decoder_o : std_logic_vector(31 downto 0); signal s_addr_decoder_o : std_logic_vector(31 downto 1);
signal s_decode_start : std_logic; signal s_decode_start : std_logic;
signal s_decode_done : std_logic; signal s_decode_done : std_logic;
signal s_decode_sel : std_logic; signal s_decode_sel : std_logic;
......
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