Maintenance scheduled 24th July -- expect downtime along that day

Commit c1ab84ba authored by Tristan Gingold's avatar Tristan Gingold

Wait until wb ack is negated before starting the second MBLT wb transaction.

parent 633d3174
......@@ -164,6 +164,9 @@ architecture rtl of vme_bus is
-- Wait for WB reply
MEMORY_REQ,
-- Wait for WB negated ack (between half MBLT transactions)
MEMORY_WAIT_ACK,
-- For read cycle, put data on the bus
DATA_TO_BUS,
......@@ -543,9 +546,9 @@ begin
s_locDataIn(31 downto 0) <= s_locDataIn(63 downto 32);
wb_stb_o <= s_card_sel;
wb_stb_o <= '0';
s_mainFSMstate <= MEMORY_REQ;
s_mainFSMstate <= MEMORY_WAIT_ACK;
else
s_mainFSMstate <= DTACK_LOW;
end if;
......@@ -571,9 +574,9 @@ begin
s_dataPhase <= '0';
s_vme_addr_reg(2) <= '1';
wb_stb_o <= s_card_sel;
wb_stb_o <= '0';
s_mainFSMstate <= MEMORY_REQ;
s_mainFSMstate <= MEMORY_WAIT_ACK;
else
s_mainFSMstate <= DATA_TO_BUS;
end if;
......@@ -582,6 +585,16 @@ begin
s_mainFSMstate <= MEMORY_REQ;
end if;
when MEMORY_WAIT_ACK =>
wb_stb_o <= '0';
if wb_ack_i = '0' then
wb_stb_o <= s_card_sel and wb_stall_i;
s_mainFSMstate <= MEMORY_REQ;
else
s_mainFSMstate <= MEMORY_WAIT_ACK;
end if;
when DATA_TO_BUS =>
VME_DTACK_OE_o <= '1';
VME_DATA_DIR_o <= s_WRITElatched_n;
......
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