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VME64x core
Commit c50928bb authored by Tristan Gingold's avatar Tristan Gingold
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MTLB: force stb to 1 after the first WB transaction.

parent c1ab84ba
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Showing with 10 additions and 17 deletions
hdl/rtl/vme_bus.vhd
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...@@ -164,8 +164,8 @@ architecture rtl of vme_bus is ...@@ -164,8 +164,8 @@ architecture rtl of vme_bus is
-- Wait for WB reply -- Wait for WB reply
MEMORY_REQ, MEMORY_REQ,
-- Wait for WB negated ack (between half MBLT transactions) -- Negate STB between half MBLT transactions
MEMORY_WAIT_ACK, MEMORY_PAUSE,
-- For read cycle, put data on the bus -- For read cycle, put data on the bus
DATA_TO_BUS, DATA_TO_BUS,
...@@ -546,9 +546,8 @@ begin ...@@ -546,9 +546,8 @@ begin
s_locDataIn(31 downto 0) <= s_locDataIn(63 downto 32); s_locDataIn(31 downto 0) <= s_locDataIn(63 downto 32);
wb_stb_o <= '0'; -- STB is 0, wait one cycle before the 2nd xfer.
s_mainFSMstate <= MEMORY_PAUSE;
s_mainFSMstate <= MEMORY_WAIT_ACK;
else else
s_mainFSMstate <= DTACK_LOW; s_mainFSMstate <= DTACK_LOW;
end if; end if;
...@@ -574,9 +573,8 @@ begin ...@@ -574,9 +573,8 @@ begin
s_dataPhase <= '0'; s_dataPhase <= '0';
s_vme_addr_reg(2) <= '1'; s_vme_addr_reg(2) <= '1';
wb_stb_o <= '0'; -- STB is 0, wait one cycle before the 2nd xfer.
s_mainFSMstate <= MEMORY_PAUSE;
s_mainFSMstate <= MEMORY_WAIT_ACK;
else else
s_mainFSMstate <= DATA_TO_BUS; s_mainFSMstate <= DATA_TO_BUS;
end if; end if;
...@@ -585,15 +583,10 @@ begin ...@@ -585,15 +583,10 @@ begin
s_mainFSMstate <= MEMORY_REQ; s_mainFSMstate <= MEMORY_REQ;
end if; end if;
when MEMORY_WAIT_ACK => when MEMORY_PAUSE =>
wb_stb_o <= '0'; -- Do not wait until ACK is 0, as ACK can be always 1.
wb_stb_o <= '1';
if wb_ack_i = '0' then s_mainFSMstate <= MEMORY_REQ;
wb_stb_o <= s_card_sel and wb_stall_i;
s_mainFSMstate <= MEMORY_REQ;
else
s_mainFSMstate <= MEMORY_WAIT_ACK;
end if;
when DATA_TO_BUS => when DATA_TO_BUS =>
VME_DTACK_OE_o <= '1'; VME_DTACK_OE_o <= '1';
......
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